WJLXT972ALC.A4 S E001 Intel, WJLXT972ALC.A4 S E001 Datasheet
WJLXT972ALC.A4 S E001
Specifications of WJLXT972ALC.A4 S E001
Related parts for WJLXT972ALC.A4 S E001
WJLXT972ALC.A4 S E001 Summary of contents
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... Intel LXT972A Single-Port 10/100 Mbps PHY Transceiver ® The Intel LXT972A Single-Port 10/100 Mbps PHY Transceiver (called hereafter the LXT972A Transceiver) directly supports both 100BASE-TX and 10BASE-T applications. The LXT972A Transceiver is IEEE compliant and provides a Media Independent Interface (MII) for easy attachment to 10/100 Media Access Controllers (MACs). The LXT972A Transceiver supports full-duplex operation at 10 Mbps and 100 Mbps ...
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... Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. ...
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... Contents 1.0 Introduction to This Document ......................................................................................... 11 1.1 Document Overview ............................................................................................11 1.2 Related Documents............................................................................................. 11 2.0 Block Diagram for Intel 3.0 Pin Assignments for Intel 4.0 Signal Descriptions for Intel 5.0 Functional Description...................................................................................................... 23 5.1 Device Overview .................................................................................................24 5.1.1 Comprehensive Functionality ................................................................. 24 5.1.2 Optimal Signal Processing Architecture ................................................. 24 5.2 Network Media / Protocol Support ...
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... Electrical Specifications ................................................................................................... 63 7.1 Electrical Parameters .......................................................................................... 63 7.2 Timing Diagrams ................................................................................................. 68 8.0 Register Definitions - IEEE Base Registers ..................................................................... 78 9.0 Register Definitions - Product-Specific Registers ............................................................ 86 ® 10.0 Intel LXT972A Transceiver Package Specifications ...................................................... 94 10.1 Top Label Markings............................................................................................. 95 11.0 Product Ordering Information ........................................................................................... 96 4 Datasheet Document Number: 249186-004 Revision Date: 25-Oct-2005 ...
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... LXT972A Transceiver RESET_L Pulse Width and Recovery Timing........ 77 35 PHY Identifier Bit Mapping ................................................................................. 81 ® 36 Intel LXT972A Transceiver LQFP Package Specifications ............................... 94 37 Sample LQFP Package - Intel 38 Sample Pb-Free (RoHS-Compliant) LQFP Package - Intel 95 39 Order Matrix for Intel Tables 1 Related Documents from Intel............................................................................. 11 ® 2 Intel LXT972A Transceiver LQFP Numeric Pin List .......................................... 14 ® ...
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... Carrier Sense, Loopback, and Collision Conditions ............................................ 41 14 4B/5B Coding ...................................................................................................... 48 15 Valid JTAG Instructions....................................................................................... 57 16 BSR Mode of Operation ...................................................................................... 58 17 Device ID Register for Intel 18 Magnetics Requirements .................................................................................... 59 19 I/O Pin Comparison of NIC and Switch RJ-45 Setups ........................................ 59 20 Absolute Maximum Ratings for Intel 21 Recommended Operating Conditions for Intel 22 Digital I/O Characteristics (Except for MII, XI/XO, and LED/CFG Pins) ...
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... Status Change Register - Address 19, Hex 13 ................................................... 90 55 LED Configuration Register - Address 20, Hex 14 .............................................. 91 56 Transmit Control Register - Address 30, Hex 1E ................................................ 93 57 Product Ordering Information ..............................................................................96 Datasheet Document Number: 249186-004 Revision Date: 25-Oct-2005 ® Intel LXT972A Single-Port 10/100 Mbps PHY Transceiver 7 ...
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... Section 11.0, “Product Ordering Information”. ® Intel LXT972A Transceiver Revision 003 Revision Date: August 6, 2002 Description Section 2.0, “Signal Descriptions”: “Intel recommends that all inputs and multi- Descriptions”. Descriptions”. Modes”. Strength”. Settings”. Instructions”. Register”. ...
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... I/O Characteristics REFCLK (table): Changed values for Input Clock Duty Cycle under Min from 40 N and under Max from 60 to 65. Datasheet Document Number: 249186-004 Revision Date: 25-Oct-2005 ® Intel LXT972A Single-Port 10/100 Mbps PHY Transceiver ® Intel LXT972A Transceiver Revision 002 Revision Date: January 2001 Description 9 ...
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... Intel LXT972A Single-Port 10/100 Mbps PHY Transceiver 10 Datasheet Document Number: 249186-004 Revision Date: 25-Oct-2005 ...
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... Chapter 2.0, “Block Diagram for Intel® LXT972A Transceiver” • Chapter 3.0, “Pin Assignments for Intel® LXT972A Transceiver” • Chapter 4.0, “Signal Descriptions for Intel® LXT972A Transceiver” • Chapter 5.0, “Functional Description” • Chapter 6.0, “Application Information” ...
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... Intel LXT972A Single-Port 10/100 Mbps PHY Transceiver 2.0 Block Diagram for Intel Figure block diagram of the LXT972A Transceiver. The LXT972A Transceiver has on-board blocks from Optimal Signal Processing™ (OSP™). ® Figure 1. Intel LXT972A Transceiver Block Diagram RESET_L Management / ...
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... Pin Assignments for Intel Figure 2 shows the pin assignments for the LXT972A Transceiver LQFP package. ® Figure 2. Pins for Intel LXT972A Transceiver 64-Pin LQFP Package 1 REFCLK/ MDDIS 4 RESET_L 5 TXSLEW0 6 TXSLEW1 7 GND 8 VCCIO GND 12 ADDR0 13 ADDR1 14 ADDR2 15 ADDR3 16 ADDR4 Datasheet Document Number: 249186-004 Revision Date: 25-Oct-2005 ® ...
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... Intel LXT972A Single-Port 10/100 Mbps PHY Transceiver Table 2 lists LXT972A Transceiver LQFP pin numbers, symbols, and pin types. ® Table 2. Intel LXT972A Transceiver LQFP Numeric Pin List (Sheet Pin 1 REFCLK/ MDDIS 4 RESET_L 5 TxSLEW0 6 TxSLEW1 7 GND 8 VCCIO GND 12 ADDR0 13 GND 14 GND ...
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... RX_CLK 53 RX_ER 54 TX_ER 55 TX_CLK 56 TX_EN 57 TXD0 58 TXD1 59 TXD2 60 TXD3 61 GND 62 COL 63 CRS 64 MDINT_L Datasheet Document Number: 249186-004 Revision Date: 25-Oct-2005 ® Intel LXT972A Single-Port 10/100 Mbps PHY Transceiver Symbol Type Input I/O I/O I/O I – – I/O I – – – – ...
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... Table 5, “Intel® LXT972A Transceiver MII Controller Interface Signal Descriptions” • Table 6, “Intel® LXT972A Transceiver Network Interface Signal Descriptions” • Table 7, “Intel® LXT972A Transceiver Standard Bus and Interface Signal Descriptions” • Table 8, “Intel® LXT972A Transceiver Configuration and LED Driver Signal Descriptions” • ...
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... COL 63 CRS Datasheet Document Number: 249186-004 Revision Date: 25-Oct-2005 ® Intel LXT972A Single-Port 10/100 Mbps PHY Transceiver Type Signal Description Transmit Data. TXD is a group of parallel data signals that are driven by the MAC. I TXD[3:0] transition synchronously with respect to TX_CLK. TXD[0] is the least-significant bit. ...
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... Intel LXT972A Single-Port 10/100 Mbps PHY Transceiver Table 5 lists signal descriptions of the LXT972A Transceiver MII controller interface pins. ® Table 5. Intel LXT972A Transceiver MII Controller Interface Signal Descriptions LQFP Symbol Pin# 3 MDDIS 43 MDC 42 MDIO 64 MDINT_L 18 Type Signal Description Management Data Disable. ...
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... Symbol Pin# 12 ADDR0 Datasheet Document Number: 249186-004 Revision Date: 25-Oct-2005 ® Intel LXT972A Single-Port 10/100 Mbps PHY Transceiver Type Signal Description Twisted-Pair Outputs, Positive and Negative. O During 100BASE-TX or 10BASE-T operation, TPOP/N pins drive IEEE 802.3 compliant pulses onto the line. Twisted-Pair Inputs, Positive and Negative. ...
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... Configuration Register. (For details, see Configuration Register - Address 20, Hex 14” on page I/O Configuration Inputs 1-3. These pins also provide initial configuration settings. (For details, see Table 12, “Hardware Configuration Settings for Intel® LXT972A Transceiver” on page 3.0 ns 3.4 ns 3.9 ns 4.4 ns Section in the Functional Table 55, “ ...
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... VCCA 9, 10 Table 10 lists signal descriptions of the LXT972A Transceiver Joint Test Action Group (JTAG) pins. Note JTAG port is not used, these pins do not need to be terminated. ® Table 10. Intel LXT972A Transceiver JTAG Test Signal Descriptions LQFP Symbol Pin# 27 TDI 28 TDO ...
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... LXT972A Transceiver. Note: • Driven High (Logic 1) • Driven Low (Logic 0) • High Impedance • Internal Pull-Down (Weak) ® Table 11. Intel LXT972A Transceiver Pin Types and Modes Modes RXD3:0 HWReset DL SFTPWRDN DL HWPWRDN High Z HZ with ...
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... Section 5.7, “100 Mbps Operation” • Section 5.8, “10 Mbps Operation” • Section 5.9, “Monitoring Operations” • Section 5.10, “Boundary Scan (JTAG 1149.1) Functions” Datasheet Document Number: 249186-004 Revision Date: 25-Oct-2005 ® Intel LXT972A Single-Port 10/100 Mbps PHY Transceiver 23 ...
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... Intel LXT972A Single-Port 10/100 Mbps PHY Transceiver 5.1 Device Overview The LXT972A Transceiver is a single-port Fast Ethernet 10/100 transceiver that supports 10 Mbps and 100 Mbps networks. It complies with applicable requirements of IEEE 802.3. It directly drives either a 100BASE-TX line or a 10BASE-T line. ...
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... Network Interface The network interface port consists of two differential signal pairs. For specific pin assignments, see Chapter 4.0, “Signal Descriptions for Intel® LXT972A The LXT972A Transceiver output drivers can generate one of the following outputs: • 100BASE-TX • ...
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... Only a transformer, RJ-45 connector, load resistor, and bypass capacitors are required to complete this interface. On the transmit side, the LXT972A Transceiver has an active internal termination and does not require external termination resistors. Intel's patented waveshaping technology shapes the outgoing signal to help reduce the need for external EMI filters. Four slew rate settings allow the designer to match the output waveform to the magnetic characteristics ...
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... MDIO Management Interface MDIO management interface topics include the following: • Section 5.2.3.1.1, “MDIO Addressing for Intel® LXT972A Transceiver” • Section 5.2.3.1.2, “MDIO Frame Structure” The LXT972A Transceiver supports the IEEE 802.3 MII Management Interface also known as the Management Data Input/Output (MDIO) Interface ...
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... Intel LXT972A Single-Port 10/100 Mbps PHY Transceiver 5.2.3.1.2 MDIO Frame Structure The physical interface consists of a data line (MDIO) and clock line (MDC). The frame structure is shown in Figure 3 and MDIO Interface timing is given in Figure 3. Management Interface Read Frame Structure MDC MDIO 32 " ...
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... Auto-negotiation complete — Speed status change — Duplex status change — Link status change • Register 19 provides the interrupt status. ® Figure 5. Intel LXT972A Transceiver MII Interrupt Logic Even X Mask Reg Even X Status Reg Force Interrupt 5.2.3.2 Hardware Control Interface The LXT972A Transceiver provides a Hardware Control Interface for applications where the MDIO is not desired ...
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... XI. The connection of a clock source to the XI pin requires the XO pin to be left open. To minimize transmit jitter, Intel recommends a crystal-based clock instead of a derived clock (that is, a PLL- based clock). A crystal is typically used in NIC applications. An external 25 MHz clock source, rather than a crystal, is frequently used in switch applications. For clock timing requirements, see Characteristics - REFCLK/XI and XO Pins” ...
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... Section 5.4.1, “MDIO Control Mode and Hardware Control Mode” • Section 5.4.2, “Reduced-Power Modes” • Section 5.4.3, “Reset for Intel® LXT972A Transceiver” • Section 5.4.4, “Hardware Configuration Settings” When the LXT972A Transceiver is first powered on, reset, or encounters a link failure state, it checks the MDIO register configuration bits to determine the line speed and operating conditions to use for the network link ...
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... Intel LXT972A Single-Port 10/100 Mbps PHY Transceiver Figure 6. Initialization Sequence for Intel MDIO Control MDIO Controlled Operation (MDIO Writes Enabled) Reset MDIO Registers to values read at H/W Control Interface at last Hardware Reset 32 ® LXT972A Transceiver Power-up or Reset Read H/W Control Interface ...
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... Software power-down control is provided by Register bit 0.11 in the Control Register. (See Table 41 on page 79.) • The network port is shut down. • The MDIO registers remain accessible. Datasheet Document Number: 249186-004 Revision Date: 25-Oct-2005 ® Intel LXT972A Single-Port 10/100 Mbps PHY Transceiver During soft power-down, the following conditions are true: 33 ...
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... Intel LXT972A Single-Port 10/100 Mbps PHY Transceiver 5.4.3 Reset for Intel The LXT972A Transceiver provides both hardware and software resets, each of which manage differently the configuration control of auto-negotiation, speed, and duplex-mode selection. For a software reset, Register bit 0. For register bit definitions used for software reset, see Table 41, “ ...
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... Hardware Configuration Settings The LXT972A Transceiver provides a hardware option to set the initial device configuration. As listed in Table 12, the hardware option uses the hardware configuration pins, the settings for which provide control bits. Table 12. Hardware Configuration Settings for Intel Desired Mode Auto- Speed Duplex Neg. ...
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... Figure 7 shows an overview of link establishment for the LXT972A Transceiver. Note: When a link is established by parallel detection, the LXT972A Transceiver sets the duplex mode to half-duplex, as defined by the IEEE 802.3 standard. ® Figure 7. Intel LXT972A Transceiver Link Establishment Overview Disable Auto-Negotiation Go To Forced Settings Done 5 ...
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... Register 6 and assuming there is valid information in Registers 5 and 8. 5.5.1.3 Controlling Auto-Negotiation When auto-negotiation is controlled by software, Intel recommends the following steps: 1. After power-up, power-down, or reset, the power-down recovery time (specified in “Intel® LXT972A Transceiver RESET_L Pulse Width and Recovery Timing” on page must be exhausted before proceeding ...
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... Intel LXT972A Single-Port 10/100 Mbps PHY Transceiver 5.6 MII Operation This section includes the following topics: • Section 5.6.1, “MII Clocks” • Section 5.6.2, “Transmit Enable” • Section 5.6.3, “Receive Data Valid” • Section 5.6.4, “Carrier Sense” ...
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... XI Datasheet Document Number: 249186-004 Revision Date: 25-Oct-2005 ® Intel LXT972A Single-Port 10/100 Mbps PHY Transceiver show the clock cycles for each mode. 2.5 MHz during auto-negotiation and 10BASE-T Data & Idle 2.5 MHz during auto-negotiation and 10BASE-T Data & Idle Constant 25 MHz 2 ...
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... Intel LXT972A Single-Port 10/100 Mbps PHY Transceiver Figure 10. Clocking for Link Down Clock Transition RX_CLK TX_CLK 5.6.2 Transmit Enable The MAC must assert TX_EN the same time as the first nibble of preamble and de-assert TX_EN after the last nibble of the packet. ...
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... Datasheet Document Number: 249186-004 Revision Date: 25-Oct-2005 ® Intel LXT972A Single-Port 10/100 Mbps PHY Transceiver Test Operational Carrier Sense Loop- ...
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... LXT972A Transceiver operational and test loopback paths. (An internal digital loopback path is not shown.) For more information on loopback functions, see Sense, Loopback, and Collision Conditions” on page ® Figure 11. Intel LXT972A Transceiver Loopback Paths Intel® LXT972A Transceiver Operational MII Loopback 5.6.7.1 Operational Loopback • ...
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... P1 P6 SFD Replaced by Start-of-Frame /J/K/ code-groups Delimiter (SFD) Start-of-Stream Delimiter (SSD) Datasheet Document Number: 249186-004 Revision Date: 25-Oct-2005 ® Intel LXT972A Single-Port 10/100 Mbps PHY Transceiver Destination and Source Packet Length Data Field Address (6 Octets each) (2 Octets) (Pad to minimum packet size ...
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... Intel LXT972A Single-Port 10/100 Mbps PHY Transceiver As shown in Figure 13, the data to the network using MLT-3 line code. MLT-3 signals received from the network are de- scrambled, decoded, and sent across the MII to the MAC. Figure 13. 100BASE-TX Data Path Standard Data Flow ...
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... RX_ER. Figure 15. 100BASE-TX Reception with Invalid Symbol RX_CLK RX_DV RXD<3:0> preamble SFD SFD DA RX_ER Datasheet Document Number: 249186-004 Revision Date: 25-Oct-2005 ® Intel LXT972A Single-Port 10/100 Mbps PHY Transceiver CRC 15, when the LXT972A Transceiver receives invalid symbols from the line ...
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... Intel LXT972A Single-Port 10/100 Mbps PHY Transceiver 5.7.2 Collision Indication Figure 16 shows normal transmission. Figure 16. 100BASE-TX Transmission with No Errors TX_CLK TX_EN TXD<3:0> P CRS COL Upon detection of a collision, the COL output is asserted and remains asserted for the duration of the collision as shown in Figure 17 ...
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... Section 5.7.3.1, “Physical Coding Sublayer” • Section 5.7.3.2, “Physical Medium Attachment Sublayer” • Section 5.7.3.3, “Twisted-Pair Physical Medium Dependent Sublayer” Figure 18 shows the LXT972A Transceiver protocol sublayers. ® Figure 18. Intel LXT972A Protocol Sublayers PCS Sublayer PMA Sublayer PMD Sublayer ...
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... Intel LXT972A Single-Port 10/100 Mbps PHY Transceiver 5.7.3.1 Physical Coding Sublayer The Physical Coding Sublayer (PCS) provides the MII interface, as well as the 4B/5B encoding/ decoding function. For 100BASE-TX operation, the PCS layer provides IDLE symbols to the PMD-layer line driver as long as TX_EN is de-asserted. ...
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... The /J/ and /K/ (SSD) code groups are always sent in pairs, and /K/ follows /J/. 3. The /T/ and /R/ (ESD) code groups are always sent in pairs, and /R/ follows /T /H/ (Error) code group is used to signal an error condition. Datasheet Document Number: 249186-004 Revision Date: 25-Oct-2005 ® Intel LXT972A Single-Port 10/100 Mbps PHY Transceiver 5B Code Name Start-of-Stream Delimiter (SSD), 2 ...
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... CRS. The PMA layer also de-asserts CRS if IDLE symbols are received without /T/R. However, in this case RX_ER is asserted for one clock cycle when CRS is de-asserted. Intel does not recommend using CRS for Interframe Gap (IFG) timing for the following reasons: • ...
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... Address 30, Hex 1E” on page output waveform to match the characteristics of the magnetics. Datasheet Document Number: 249186-004 Revision Date: 25-Oct-2005 ® Intel LXT972A Single-Port 10/100 Mbps PHY Transceiver Table 56, “Transmit Control Register - 93.) The slew-rate mechanism allows the designer to optimize the 51 ...
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... Intel LXT972A Single-Port 10/100 Mbps PHY Transceiver 5.8 10 Mbps Operation The LXT972A Transceiver operates as a standard 10BASE-T transceiver and LXT972A supports standard 10 Mbps functions. During 10BASE-T operation, the LXT972A Transceiver transmits and receives Manchester-encoded data across the network link. When the MAC is not actively transmitting data, the LXT972A Transceiver drives link pulses onto the line ...
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... When polarity reversal is detected in 10BASE-T operation, register 17.5 is set to 1. (For details, see bit 17.5 in Datasheet Document Number: 249186-004 Revision Date: 25-Oct-2005 ® Intel LXT972A Single-Port 10/100 Mbps PHY Transceiver Figure 27, “Intel® LXT972A Transceiver 72. Table 52, “Status Register #2 - Address 17, Hex 11” on page 88.) 53 ...
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... Intel LXT972A Single-Port 10/100 Mbps PHY Transceiver 5.9 Monitoring Operations 5.9.1 Monitoring Auto-Negotiation Auto-negotiation can be monitored as follows: • Register bit 17.7 is set to ‘1’ once the auto-negotiation process is completed. • Register bits 1.2 and 17.10 are set to ‘1’ once the link is established. ...
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... Max current rating) as required by the hardware configuration. For details, see the discussion of Datasheet Document Number: 249186-004 Revision Date: 25-Oct-2005 ® Intel LXT972A Single-Port 10/100 Mbps PHY Transceiver 91) to indicate one of the following “Hardware Configuration Settings” on page (Table 55, “LED 35. ...
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... Intel LXT972A Single-Port 10/100 Mbps PHY Transceiver 5.9.4 LED Pulse Stretching The LED Configuration Register also provides optional LED pulse stretching to 30, 60, or 100 ms. The pulse stretch time is extended further if the event occurs again during this pulse stretch period. When an event such as receiving a packet occurs, the event is edge detected and it starts the stretch timer ...
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... Boundary Scan (JTAG 1149.1) Functions The LXT972A Transceiver includes a IEEE 1149.1 boundary scan test port for board level testing. All digital input, output, and input/output pins are accessible. Note: For the related BSDL file, contact your local sales office or access the Intel website (www.intel.com). 5.10.1 Boundary Scan Interface The boundary scan interface consists of five pins (TMS, TDI, TDO, TRST_L, and TCK) ...
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... Table 17. Device ID Register for Intel Bits 31:28 Bits 27:12 Version Part ID (Hex) XXXX 1. The JEDEC 8-bit identifier. The MSB is for parity and is ignored. The Intel JEDEC (1111 1110), which becomes 111 1110. 58 Table 16 lists the four BSR modes of operation. Capture Shift Update ® ...
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... Table 19. I/O Pin Comparison of NIC and Switch RJ-45 Setups Symbol TPIP TPIN TPOP TPON Datasheet Document Number: 249186-004 Revision Date: 25-Oct-2005 ® Intel LXT972A Single-Port 10/100 Mbps PHY Transceiver Min Nom Max – – – – 0.0 ...
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... Intel LXT972A Single-Port 10/100 Mbps PHY Transceiver Figure 20 shows the LXT972A Transceiver in a typical twisted-pair interface, with the RJ-45 connections crossed over for a Switch configuration. ® Figure 20. Intel LXT972A Transceiver Typical Twisted-Pair Interface - Switch TPOP Intel® LXT972A Transceiver TPON VCCA 1 ...
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... Figure 21 shows the LXT972A Transceiver in a typical twisted-pair interface, with the RJ-45 connections configured for a NIC application. ® Figure 21. Intel LXT972A Transceiver Typical Twisted-Pair Interface - NIC Intel® LXT972A Transceiver SD/TP_L 1. Center tap current may be supplied from 3.3 V VCCA as shown. Additional power savings may be realized by supplying the center tap from a 2 ...
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... Intel LXT972A Single-Port 10/100 Mbps PHY Transceiver Figure 22 shows a typical media independent interface (MII) for the LXT972A Transceiver. ® Figure 22. Intel LXT972A Transceiver Typical Media Independent Interface MAC 62 TX_EN TX_ER TXD[3:0] TX_CLK RX_CLK Intel® LXT972A RX_DV RX_ER Transceiver RXD[3:0] ...
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... Exceeding the absolute maximum rating values may cause permanent damage. • Functional operation under these conditions is not implied. • Exposure to maximum rating conditions for extended periods may affect device reliability. Table 20. Absolute Maximum Ratings for Intel Parameter Supply Voltage Storage Temperature Table 21 lists the recommended operating conditions for the LXT972A Transceiver ...
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... Intel LXT972A Single-Port 10/100 Mbps PHY Transceiver Table 22 lists digital I/O characteristics for all pins except the MII, XI/XO, and LED/CFG pins. Table 22. Digital I/O Characteristics (Except for MII, XI/XO, and LED/CFG Pins) Parameter Input Low voltage Input High voltage ...
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... Table 25. I/O Characteristics - LED/CFG Pins Parameter Input Low Voltage Input High Voltage Input Current Output Low Voltage Output High Voltage Datasheet Document Number: 249186-004 Revision Date: 25-Oct-2005 ® Intel LXT972A Single-Port 10/100 Mbps PHY Transceiver 1 Symbol Min Typ V – – 2.0 – ...
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... Intel LXT972A Single-Port 10/100 Mbps PHY Transceiver Table 26 lists the 100BASE-TX characteristics. Table 26. 100BASE-TX Transceiver Characteristics Parameter Peak differential output voltage Signal amplitude symmetry Signal rise/fall time Rise/fall time symmetry Duty cycle distortion Overshoot/Undershoot Jitter (measured differentially) 1. Typical values are at 25 °C and are for design aid only, not guaranteed, and not subject to production testing. 2. Measured at the line side of the transformer, line replaced by 100 Ω ...
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... Table 29 lists the thermal characteristics. ® Table 29. Intel LXT972A Transceiver Thermal Characteristics Parameter Package Theta-JA Theta-JC Psi - JT Datasheet Document Number: 249186-004 Revision Date: 25-Oct-2005 ® Intel LXT972A Single-Port 10/100 Mbps PHY Transceiver LXT972A Transceiver x1 LQFP 58 C/W 27 C/W 3.4 C/W 67 ...
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... TPI CRS RX_DV RXD[3:0] RX_CLK COL Note: Timing diagram depicts 4B mode. ® Table 30. Intel LXT972A Transceiver 100BASE-TX Receive Timing Parameters Parameter RXD[3:0], RX_DV, RX_ER RX_CLK High RXD[3:0], RX_DV, RX_ER hold from RX_CLK High CRS asserted to RXD[3:0], RX_DV Receive start of “J” to CRS asserted Receive start of “ ...
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... Figure 24. Intel LXT972A Transceiver 100BASE-TX Transmit Timing TXCLK TX_EN TXD[3:0] TPO CRS Note: Timing diagram depicts 4B mode. Figure 24 does not show the TX_ER signal. . ® Table 31. Intel LXT972A Transceiver 100BASE-TX Transmit Timing Parameters Parameter TXD[3:0], TX_EN, TX_ER setup to TX_CLK High ...
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... LXT972A Transceiver 10BASE-T Receive Timing RX_CLK RXD, RX_DV, RX_ER CRS TPI COL ® Table 32. Intel LXT972A Transceiver 10BASE-T Receive Timing Parameter RXD, RX_DV, TX_ER (not shown in figure). Setup to RX_CLK High RXD, RX_DV, RX_ER Hold from RX_CLK High TPIP RXD out (Rx latency) CRS asserted to RXD, RX_DV, ...
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... Figure 26. Intel LXT972A Transceiver 10BASE-T Transmit Timing TX_CLK TXD, TX_EN, TX_ER CRS TPO ® Table 33. Intel LXT972A Transceiver 10BASE-T Transmit Timing Parameters Parameter TXD, TX_EN, TX_ER setup to TX_CLK High TXD, TX_EN, TX_ER hold from TX_CLK High TX_EN sampled to CRS asserted ...
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... LXT972A Transceiver 10BASE-T Jabber and Unjabber Timing TX_EN TXD COL ® Table 34. Intel LXT972A Transceiver 10BASE-T Jabber and Unjabber Timing Parameter Maximum transmit time Unjabber time 1. Typical values are at 25 °C and are for design aid only, not guaranteed, and not subject to production testing ...
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... Figure 28. Intel LXT972A Transceiver 10BASE-T SQE (Heartbeat) Timing TX_CLK TX_EN COL ® Table 35. Intel LXT972A Transceiver 10BASE-T SQE (Heartbeat) Timing Parameter COL (SQE) Delay after TX_EN off COL (SQE) Pulse duration 1. Typical values are at 25 °C and are for design aid only, not guaranteed, and not subject to production testing ...
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... LXT972A Transceiver Auto-Negotiation and Fast Link Pulse Timing TPOP ® Figure 30. Intel LXT972A Transceiver Fast Link Pulse Timing TPOP ® Table 36. Intel LXT972A Transceiver Auto-Negotiation / Fast Link Pulse Timing Parameter Clock/Data pulse width Clock pulse to Data pulse Clock pulse to Clock pulse FLP burst width ...
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... LXT972A Transceiver MDIO Input Timing MDC MDIO ® Figure 32. Intel LXT972A Transceiver MDIO Output Timing MDC MDIO ® Table 37. Intel LXT972A Transceiver MDIO Timing Parameter MDIO setup before MDC, sourced by STA MDIO hold after MDC, sourced by STA MDC to MDIO output delay, sourced by PHY MDC period 1. Typical values are at 25° ...
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... Figure 33. Intel LXT972A Transceiver Power-Up Timing VCC MDIO, and so on ® Table 38. Intel LXT972A Transceiver Power-Up Timing Parameter Voltage threshold 2 Power Up delay 1. Typical values are at 25° C and are for design aid only, not guaranteed, and not subject to production testing. ...
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... Figure 34. Intel LXT972A Transceiver RESET_L Pulse Width and Recovery Timing RESET_L MDIO, and so on ® Table 39. Intel LXT972A Transceiver RESET_L Pulse Width and Recovery Timing Parameter RESET_L pulse width RESET_L recovery delay 1. Typical values are at 25° C and are for design aid only, not guaranteed, and not subject to production testing ...
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... Intel LXT972A Single-Port 10/100 Mbps PHY Transceiver 8.0 Register Definitions - IEEE Base Registers This chapter includes definitions for the IEEE base registers used by the LXT972A Transceiver. Chapter 9.0, “Register Definitions - Product-Specific Registers” product-specific LXT972A Transceiver registers, which are defined in accordance with the IEEE 802 ...
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... Some bits have their default values determined at reset by hardware configuration pins. For default details for these bits, see Datasheet Document Number: 249186-004 Revision Date: 25-Oct-2005 ® Intel LXT972A Single-Port 10/100 Mbps PHY Transceiver Description 0 = Normal operation 1 = PHY reset 0 = Disable loopback mode 1 = Enable loopback mode 0 ...
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... Intel LXT972A Single-Port 10/100 Mbps PHY Transceiver Table 42 lists MII status register bits. Table 42. MII Status Register #1 - Address 1, Hex 1 Bit Name 100BASE-T4 1.15 Not Supported 1.14 100BASE-X Full-Duplex 1.13 100BASE-X Half-Duplex 1.12 10 Mbps Full-Duplex 1.11 10 Mbps Half-Duplex 100BASE-T2 Full- Duplex 1 ...
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... RO = Read Only Figure 35. PHY Identifier Bit Mapping PHY ID Register #1 (Address 2) = 0013 Note: The Intel OUI is 00207B hex Datasheet Document Number: 249186-004 Revision Date: 25-Oct-2005 ® Intel LXT972A Single-Port 10/100 Mbps PHY Transceiver 44, see Figure 35. Description The PHY identifier is composed of bits 3 through 18 of the Organizationally Unique Identifier (OUI) ...
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... Intel LXT972A Single-Port 10/100 Mbps PHY Transceiver Table 45 lists auto-negotiation advertisement bits. Table 45. Auto-Negotiation Advertisement Register - Address 4, Hex 4 Bit Name 4.15 Next Page 4.14 Reserved 4.13 Remote Fault 4.12 Reserved Asymmetric 4.11 Pause 4.10 Pause 4.9 100BASE-T4 100BASE-TX full-duplex 4.8 ...
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... S<4:0> Read Only Datasheet Document Number: 249186-004 Revision Date: 25-Oct-2005 ® Intel LXT972A Single-Port 10/100 Mbps PHY Transceiver Description 0 = Link Partner has no ability to send multiple pages Link Partner has ability to send multiple pages Link Partner has not received Link Code Word from the LXT972A Transceiver ...
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... Intel LXT972A Single-Port 10/100 Mbps PHY Transceiver Table 47 lists auto-negotiation expansion bits. Table 47. Auto-Negotiation Expansion - Address 6, Hex 6 Bit Name 6.15:6 Reserved 6.5 Base Page Parallel 6.4 Detection Fault Link Partner 6.3 Next Page Able 6.2 Next Page Able 6.1 Page Received Link Partner A/N 6 ...
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... Code Field Read Only. Datasheet Document Number: 249186-004 Revision Date: 25-Oct-2005 ® Intel LXT972A Single-Port 10/100 Mbps PHY Transceiver Description 0 = Last page 1 = Additional next pages follow Ignore when read Register bits 7.10:0 are user defined Register bits 7.10.0 follow IEEE message page format ...
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... Intel LXT972A Single-Port 10/100 Mbps PHY Transceiver 9.0 Register Definitions - Product-Specific Registers This chapter includes definitions of product-specific LXT972A Transceiver registers that are defined in accordance with the IEEE 802.3 standard for adding unique device functions. (For definitions of the IEEE base registers used by the LXT972A Transceiver, see “ ...
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... Reserved 1. R/W = Read /Write Datasheet Document Number: 249186-004 Revision Date: 25-Oct-2005 ® Intel LXT972A Single-Port 10/100 Mbps PHY Transceiver Description Write as ‘0’. Ignore on Read Normal operation 1 = Force Link pass 0 = Normal operation 1 = Disable Twisted Pair transmitter 0 = Normal operation 1 = Bypass Scrambler and Descrambler Write as ‘ ...
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... Intel LXT972A Single-Port 10/100 Mbps PHY Transceiver Table 52 lists register #2 status bits. Table 52. Status Register #2 - Address 17, Hex 11 Bit Name 17.15 Reserved 17.14 10/100 Mode 17.13 Transmit Status 17.12 Receive Status 17.11 Collision Status 17.10 Link 17.9 Duplex Mode 17.8 Auto-Negotiation Auto-Negotiation 17 ...
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... TINT 1. R/W = Read /Write Datasheet Document Number: 249186-004 Revision Date: 25-Oct-2005 ® Intel LXT972A Single-Port 10/100 Mbps PHY Transceiver Description Write as ‘0’. Ignore on Read. Write as ‘0’. Ignore on Read. Mask for Auto Negotiate Complete not allow event to cause interrupt. ...
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... Intel LXT972A Single-Port 10/100 Mbps PHY Transceiver Table 54 lists status change bits. Table 54. Status Change Register - Address 19, Hex 13 Bit Name 19.15:9 Reserved 19.8 Reserved 19.7 ANDONE 19.6 SPEEDCHG 19.5 DUPLEXCHG 19.4 LINKCHG 19.3 Reserved 19.2 MDINT_L 19.1 Reserved 19.0 Reserved 1 ...
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... Collision status is the secondary LED driver. The LED changes state (blinks) when a collision occurs. 5. Values are approximations. Not guaranteed or production tested. Datasheet Document Number: 249186-004 Revision Date: 25-Oct-2005 ® Intel LXT972A Single-Port 10/100 Mbps PHY Transceiver Description 0000 = Display Speed Status (Continuous, Default) 0001 = Display Transmit Status (Stretched) 0010 = Display Receive Status (Stretched) ...
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... Intel LXT972A Single-Port 10/100 Mbps PHY Transceiver Table 55. LED Configuration Register - Address 20, Hex 14 (Sheet Bit Name LED3 20.7:4 Programming bits 20.3:2 LEDFREQ PULSE- 20.1 STRETCH 20.0 Reserved 1. R/W = Read /Write Read Only Latching High 2. Link status is the primary LED driver. The LED is asserted (solid ON) when the link is up. ...
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... R/W = Read/Write 3. Latch State during Reset is based on the state of hardware configuration pins at RESET_L. Datasheet Document Number: 249186-004 Revision Date: 25-Oct-2005 ® Intel LXT972A Single-Port 10/100 Mbps PHY Transceiver Description Write as ‘0’. Ignore on Read. Transmit Low Power 0 = Normal transmission Forces the transmitter into low power mode. ...
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... LXT972A Transceiver Package Specifications ® Figure 36. Intel LXT972A Transceiver LQFP Package Specifications 64-Pin Low-Profile Quad Flat Pack NOTE: The package figure is generic and used only to demonstrate package dimensions. (The figure does not show the same number of pins as for the Intel Millimeters Dim Min Max A – ...
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... LQFP package for the LXT972A Transceiver. Note: In contrast to the Pb-Free (RoHS-compliant) LQFP package, the non-RoHS-compliant package does not have the “e3” symbol in the last line of the package label. Figure 37. Sample LQFP Package - Intel Pin 1 Figure 38 shows a sample Pb-Free (RoHS-compliant) LQFP package for the LXT972A Transceiver ...
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... Intel LXT972A Single-Port 10/100 Mbps PHY Transceiver 11.0 Product Ordering Information Table 57 lists product ordering information for the LXT972A Transceiver. Table 57. Product Ordering Information Number DJLXT972ALC.A4 WJLXT972ALC.A4 96 Package Revision Pin Count Type A4 LQFP 64 A4 LQFP 64 RoHS Compliant No Yes Datasheet Document Number: 249186-004 ...
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... Figure 39 shows an order matrix with sample information for ordering an LXT972A Transceiver. Figure 39. Order Matrix for Intel DJ Datasheet Document Number: 249186-004 Revision Date: 25-Oct-2005 ® Intel LXT972A Single-Port 10/100 Mbps PHY Transceiver ® LXT972A Transceiver LXT 972A Product Revision Alphanumeric characters Temperature Range Ambient (0 – ...