WJLXT972ALC.A4 S E001 Intel, WJLXT972ALC.A4 S E001 Datasheet - Page 3

• Manufacturer Part Number: WJLXT972ALC.A4 S E001
• Manufacturer: Intel

Specifications of WJLXT972ALC.A4 S E001

• Lead Free Status / Rohs Status: Compliant

Contents
1.0
2.0
3.0
4.0
5.0
Datasheet
Document Number: 249186-004
Revision Date: 25-Oct-2005
Introduction to This Document ......................................................................................... 11
1.1
1.2
Block Diagram for Intel
Pin Assignments for Intel
Signal Descriptions for Intel
Functional Description...................................................................................................... 23
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
Document Overview ............................................................................................11
Related Documents............................................................................................. 11
Device Overview .................................................................................................24
5.1.1
5.1.2
Network Media / Protocol Support.......................................................................25
5.2.1
5.2.2
5.2.3
Operating Requirements .....................................................................................30
5.3.1
5.3.2
Initialization.......................................................................................................... 31
5.4.1
5.4.2
5.4.3
5.4.4
Establishing Link .................................................................................................36
5.5.1
5.5.2
MII Operation....................................................................................................... 38
5.6.1
5.6.2
5.6.3
5.6.4
5.6.5
5.6.6
5.6.7
100 Mbps Operation ............................................................................................43
5.7.1
5.7.2
5.7.3
10 Mbps Operation.............................................................................................. 52
5.8.1
5.8.2
5.8.3
5.8.4
5.8.5
Comprehensive Functionality ................................................................. 24
Optimal Signal Processing Architecture ................................................. 24
10/100 Network Interface .......................................................................25
MII Data Interface ................................................................................... 27
Configuration Management Interface ..................................................... 27
Power Requirements ..............................................................................30
Clock Requirements ............................................................................... 30
MDIO Control Mode and Hardware Control Mode .................................33
Reduced-Power Modes .......................................................................... 33
Reset for Intel
Hardware Configuration Settings ...........................................................35
Auto-Negotiation.....................................................................................36
Parallel Detection ................................................................................... 37
MII Clocks............................................................................................... 39
Transmit Enable .....................................................................................40
Receive Data Valid ................................................................................. 40
Carrier Sense ......................................................................................... 41
Error Signals........................................................................................... 41
Collision .................................................................................................. 41
Loopback................................................................................................ 42
100BASE-X Network Operations ...........................................................43
Collision Indication ................................................................................. 46
100BASE-X Protocol Sublayer Operations ............................................ 47
10BASE-T Preamble Handling ............................................................... 52
10BASE-T Carrier Sense .......................................................................52
10BASE-T Dribble Bits ........................................................................... 52
10BASE-T Link Integrity Test ................................................................. 53
Link Failure ............................................................................................. 53
®
LXT972A Transceiver ............................................................... 12
®
LXT972A Transceiver............................................................ 13
®
Intel
LXT972A Transceiver........................................................ 16
®
LXT972A Transceiver ................................................... 34
®
LXT972A Single-Port 10/100 Mbps PHY Transceiver
3