WJLXT972ALC.A4 S E001 Intel, WJLXT972ALC.A4 S E001 Datasheet - Page 84

• Manufacturer Part Number: WJLXT972ALC.A4 S E001
• Manufacturer: Intel

Specifications of WJLXT972ALC.A4 S E001

• Lead Free Status / Rohs Status: Compliant

Intel
84
Table 47. Auto-Negotiation Expansion - Address 6, Hex 6
®
LXT972A Single-Port 10/100 Mbps PHY Transceiver
Table 47
1. RO = Read Only LH = Latching High
6.15:6
Bit
6.5
6.4
6.3
6.2
6.1
6.0
lists auto-negotiation expansion bits.
Reserved
Base Page
Parallel
Detection Fault
Link Partner
Next Page Able
Next Page Able
Page Received
Link Partner A/N
Able
Name
Ignore when read.
This bit indicates the status of the auto-negotiation
variable base page. It flags synchronization with the
auto-negotiation state diagram, allowing detection of
interrupted links. This bit is used only if Register bit
16.1 (that is, Alternate NP feature) is set.
0 = Base page = False (base page not received)
1 = Base page = True (base page received)
0 = Parallel detection fault has not occurred.
1 = Parallel detection fault has occurred.
0 = Link partner is not next page able.
1 = Link partner is next page able.
0 = Local device is not next page able.
1 = Local device is next page able.
This bit is cleared on Read. If Register bit 16.1 is set,
the Page Received bit is also cleared when either
mr_page_rx = false or transmit_disable = true.
1 = Indicates a new page is received and the received
0 = Link partner is not auto-negotiation able.
1 = Link partner is auto-negotiation able.
code word is loaded into Register 5 (Base Pages)
or Register 8 (Next Pages) as specified in Clause
28 of IEEE 802.3.
Description
Document Number: 249186-004
Revision Date: 25-Oct-2005
RO/LH
RO/LH
RO/LH
Type
RO
RO
RO
RO
1
Datasheet
Default
0
0
0
0
1
0
0