E28F320J3A110

Manufacturer Part NumberE28F320J3A110
ManufacturerIntel
E28F320J3A110 datasheet
 


Specifications of E28F320J3A110

Cell TypeNORDensity32Mb
Access Time (max)110nsInterface TypeParallel
Boot TypeNot RequiredAddress Bus22/21Bit
Operating Supply Voltage (typ)3/3.3VOperating Temp Range-40C to 85C
Package TypeTSOPProgram/erase Volt (typ)2.7 to 3.6V
Sync/asyncAsynchronousOperating Temperature ClassificationIndustrial
Operating Supply Voltage (min)2.7VOperating Supply Voltage (max)3.6V
Word Size8/16BitNumber Of Words4M/2M
MountingSurface MountPin Count56
Lead Free Status / Rohs StatusNot Compliant  
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Intel StrataFlash
256-Mbit (x8/x16)
Product Features
Performance
— 110/115/120/150 ns Initial Access Speed
— 125 ns Initial Access Speed (256 Mbit
density only)
— 25 ns Asynchronous Page mode Reads
— 30 ns Asynchronous Page mode Reads
(256Mbit density only)
— 32-Byte Write Buffer
—6.8 µs per byte effective
programming time
Software
— Program and Erase suspend support
— Flash Data Integrator (FDI), Common
Flash Interface (CFI) Compatible
Security
— 128-bit Protection Register
—64-bit Unique Device Identifier
—64-bit User Programmable OTP Cells
— Absolute Protection with V
PEN
— Individual Block Locking
— Block Erase/Program Lockout during
Power Transitions
Capitalizing on Intel’s 0.25 and 0.18 micron, two-bit-per-cell technology, the Intel StrataFlash
device provides 2X the bits in 1X the space, with new features for mainstream performance. Offered in 256-
Mbit (32-Mbyte), 128-Mbit (16-Mbyte), 64-Mbit, and 32-Mbit densities, the J3 device brings reliable, two-bit-
per-cell storage technology to the flash market segment. Benefits include more density in less space, high-speed
interface, lowest cost-per-bit NOR device, support for code and data storage, and easy migration to future
devices.
Using the same NOR-based ETOX™ technology as Intel’s one-bit-per-cell products, the J3 device takes
advantage of over one billion units of flash manufacturing experience since 1987. As a result, J3 components
are ideal for code and data applications where high density and low cost are required. Examples include
networking, telecommunications, digital set top boxes, audio recording, and digital imaging.
By applying FlashFile™ memory family pinouts, J3 memory components allow easy design migrations from
existing Word-Wide FlashFile memory (28F160S3 and 28F320S3), and first generation Intel StrataFlash
memory (28F640J5 and 28F320J5) devices.
J3 memory components deliver a new generation of forward-compatible software support. By using the
Common Flash Interface (CFI) and the Scalable Command Set (SCS), customers can take advantage of density
upgrades and optimized write capabilities of future Intel StrataFlash
0.18 micron ETOX™ VII (J3C) and 0.25 micron ETOX™ VI (J3A) process technology, the J3 memory device
provides the highest levels of quality and reliability.
Notice: This document contains information on new products in production. The specifications are
subject to change without notice. Verify with your local Intel sales office that you have the latest
datasheet before finalizing a design.
®
Memory (J3)
Architecture
— Multi-Level Cell Technology: High
Density at Low Cost
— High-Density Symmetrical 128-Kbyte
Blocks
—256 Mbit (256 Blocks) (0.18µm only)
—128 Mbit (128 Blocks)
—64 Mbit (64 Blocks)
—32 Mbit (32 Blocks)
Quality and Reliability
— Operating Temperature:
-40 °C to +85 °C
— 100K Minimum Erase Cycles per Block
— 0.18 µm ETOX™ VII Process (J3C)
— 0.25 µm ETOX™ VI Process (J3A)
Packaging and Voltage
— 56-Lead TSOP Package
— 64-Ball Intel
Easy BGA Package
®
— Lead-free packages available
— 48-Ball Intel
VF BGA Package (32 and
®
= GND
64 Mbit) (x16 only)
— V
= 2.7 V to 3.6 V
CC
— V
= 2.7 V to 3.6 V
CCQ
®
memory devices. Manufactured on Intel
Order Number: 290667-021
Datasheet
®
Memory (J3)
®
®
March 2005

E28F320J3A110 Summary of contents

  • Page 1

    ... ETOX™ VII (J3C) and 0.25 micron ETOX™ VI (J3A) process technology, the J3 memory device provides the highest levels of quality and reliability. Notice: This document contains information on new products in production. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design. ® ...

  • Page 2

    ... Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800- 548-4725 or by visiting Intel's website at http://www.intel.com. ...

  • Page 3

    Contents 1.0 Introduction....................................................................................................................................7 1.1 Nomenclature .......................................................................................................................7 1.2 Conventions..........................................................................................................................7 2.0 Functional Overview .....................................................................................................................8 2.1 Block Diagram ......................................................................................................................9 2.2 Memory Map .......................................................................................................................10 3.0 Package Information ...................................................................................................................11 3.1 56-Lead TSOP Package .....................................................................................................11 3.2 Easy BGA (J3) Package .....................................................................................................12 3.3 VF-BGA (J3) Package ........................................................................................................13 ...

  • Page 4

    ... Programming the Protection Register.................................................................... 47 13.3.3 Locking the Protection Register............................................................................. 47 13.4 Array Protection .................................................................................................................. 49 14.0 Special Modes.............................................................................................................................. 50 14.1 Set Read Configuration Register Command ...................................................................... 50 14.2 Status (STS) ....................................................................................................................... 50 Appendix A Common Flash Interface.................................................................................................52 Appendix B Flow Charts ......................................................................................................................59 Appendix C Design Considerations ...................................................................................................68 Appendix D Additional Information ....................................................................................................70 Appendix E Ordering Information.......................................................................................................71 4 Datasheet ...

  • Page 5

    Revision History Date of Version Revision 07/07/99 -001 08/03/99 -002 09/07/99 -003 12/16/99 -004 03/16/00 -005 06/26/00 -006 2/15/01 -007 04/13/01 -008 Datasheet Description Original Version A –A indicated on block diagram 0 2 Changed Minimum Block Erase time,I OL ...

  • Page 6

    ... Description ® Added Figure 4, 3 Volt Intel StrataFlash ® Added Figure 5, 3 Volt Intel StrataFlash Specifications Updated Operating Temperature Range to Extended (Section 6.1 and Table 22) Reduced ns. Reduced t EHQZ WHEH Added parameter values for –40 °C operation to Lock-Bit and Suspend Latency ...

  • Page 7

    ... Introduction This document describes the Intel StrataFlash device features, operations, and specifications. 1.1 Nomenclature AMIN: AMIN = A0 for x8 AMIN = A1 for x16 AMAX: 32 Mbit 64 Mbit 128 Mbit 256 Mbit Block: A group of flash cells that share common erase circuitry and erase simultaneously Clear: ...

  • Page 8

    ... J3 (x8/x16) 2.0 Functional Overview The Intel StrataFlash 16Mwords (256-Mbit, available on the 0.18µm lithography process only), 16 Mbytes or 8 Mwords (128-Mbit), 8 Mbytes or 4 Mwords (64-Mbit), and 4 Mbytes or 2 Mwords (32-Mbit). These devices can be accessed 16-bit words. The 128-Mbit device is organized as one-hundred- twenty-eight 128-Kbyte (131,072 bytes) erase blocks ...

  • Page 9

    ... RP# going high until data outputs are valid. Likewise, the device has a wake time (t ) from RP#-high until writes to the CUI are recognized. With RP PHWL and the Status Register is cleared. 2.1 Block Diagram Figure 1. 3 Volt Intel StrataFlash VCCQ A[2:0] Y-Decoder A[MAX:MIN] Input Buffer Address ...

  • Page 10

    ... J3 (x8/x16) 2.2 Memory Map Figure 2. Intel StrataFlash A[24-0]: 256 Mbit A [23-0]:128 Mbit A [22-0]: 64 Mbit A [21-0]: 32 Mbit 1FFFFFF 128-Kbyte Block 1FE0000 0FFFFFF 128-Kbyte Block 0FE0000 07FFFFF 128-Kbyte Block 07E0000 03FFFFF 128-Kbyte Block 03E0000 003FFFF 128-Kbyte Block 0020000 001FFFF 128-Kbyte Block ...

  • Page 11

    Package Information 3.1 56-Lead TSOP Package Figure 3. 56-Lead TSOP Package Drawing and Specifications Z Pin 1 See Detail A Detail A Table 1. 56-Lead TSOP Dimension Table Sym Package Height A Standoff A 1 Package Body Thickness A ...

  • Page 12

    ... Seating Plane Coplanarity Corner to Ball A1 Distance Along D (32/64/128/256 Mb) Corner to Ball A1 Distance Along E (32/64/128 Mb) Corner to Ball A1 Distance Along E (256 Mb) NOTES: 1. For Daisy Chain Evaluation Unit information refer to the Intel Flash Memory Packaging Technology Web page at; www.intel.com/design/packtech/index.htm 2. For Packaging Shipping Media information see www.intel.com/design/packtech/index.htm 12 ® ...

  • Page 13

    ... Se a tin ity NOTES: 1. For Daisy Chain Evaluation Unit information refer to the Intel Flash Memory Packaging Technology Web page at; www.intel.com/design/packtech/index.htm 2. For Packaging Shipping Media information refer to the Intel Flash Memory Packaging Technology Web page at; www.intel.com/design/packtech/index.htm Datasheet ® Memory (J3) VF BGA Mechanical Specifications ...

  • Page 14

    ... Intel StrataFlash memory is available in three package types. Each density of the J3C is supported on both 64-ball Easy BGA and 56-lead Thin Small Outline Package (TSOP) packages. A 48-ball VF BGA package is available on 32 and 64 Mbit devices. pinouts. 4.1 Easy BGA Ballout (32/64/128/256 Mbit) Figure 6. Intel StrataFlash ...

  • Page 15

    ... TSOP (32/64/128/256 Mbit) Figure 7. Intel StrataFlash 28F160S3 28F320J5 RP GND NOTES: 1. A22 exists on 64-, 128- and 256-Mbit densities. On 32-Mbit densities this signal is a no-connect (NC). 2. A23 exists on 128-Mbit densities. On 32- and 64-Mbit densities this signal is a no-connect (NC). 3. A24 exists on 256-Mbit densities. On 32-, 64- and 128-Mbit densities this signal is a no-connect (NC). ...

  • Page 16

    ... ERASE / PROGRAM / BLOCK LOCK ENABLE: For erasing array blocks, programming data, or configuring lock-bits. VPEN Input With V PEN CORE POWER SUPPLY: Core (logic) source voltage. Writes to the flash array are inhibited VCC Power when V VCCQ Power I/O POWER SUPPLY: I/O Output-driver source voltage. This ball can be tied to V ...

  • Page 17

    ... GND Supply GROUND: Do not float any ground signals. NC — NO CONNECT: Lead is not internally connected; it may be driven or floated. RESERVED for FUTURE USE: Balls designated as RFU are reserved by Intel for future device RFU — functionality and enhancement. Datasheet 256-Mbit J3 (x8/x16) Name and Function ...

  • Page 18

    ... Absolute Maximum Ratings This datasheet contains information on new products in production. The specifications are subject to change without notice. Verify with your local Intel Sales office that you have the latest datasheet before finalizing a design. Absolute maximum ratings are shown in Warning: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage. ...

  • Page 19

    Electrical Specifications 6.1 DC Current Characteristics Table 6. DC Current Characteristics (Sheet VCCQ VCC Symbol Parameter I Input and V Load Current LI PEN I Output Leakage Current Standby Current CCS CC I ...

  • Page 20

    ... Current NOTES: 1. All currents are in RMS unless otherwise noted. These currents are valid for all product versions (packages and speeds). Contact Intel’s Application Support Hotline or your local sales office for information about typical specifications. 2. Includes STS. 3. CMOS inputs are either V ± ...

  • Page 21

    Table 7. DC Voltage Characteristics Symbol V during Block Erase, PEN V PENH Program, or Lock-Bit Operations V V Lockout Voltage LKO CC NOTES: 1. Includes STS. 2. Sampled, not 100% tested. 3. Block erases, programming, and lock-bit configurations are ...

  • Page 22

    J3 (x8/x16) 7.0 AC Characteristics 7.1 Read Operations Table 8. Read Operations (Sheet Asynchronous Specifications (All units in ns unless otherwise noted) Speed Bin # Sym Parameter Density 32 Mbit 64 Mbit Read/Write R1 t AVAV ...

  • Page 23

    ... Figure 15, “Transient Input/Output Reference Waveform for VCCQ = 2.7 V–3.6 V” on page 29 and Figure 16, “Transient Equivalent Testing Load Circuit” on page 30 for testing characteristics. 4. When reading the flash array a faster t Status Register reads, query reads, or device identifier reads. 5. Sampled, not 100% tested. 6. For devices configured to standard word/byte read mode, R15 ( ...

  • Page 24

    ... CE0, CE1, or CE2 that enables the device first edge of CE0, CE1, or CE2 that disables the device (see 2. When reading the flash array a faster t Register reads, query reads, or device identifier reads). Figure 10. 4-Word Page Mode Read Waveform ...

  • Page 25

    Figure 11. 8-word Asynchronous Page Mode Read A[MAX:4] [A] A[3:1] [A] CEx [E] OE# [G] WE# [W] D[15:0] [Q] RP# [P] BYTE# NOTES low is defined as the last edge of CE0, CE1, or CE2 that enables the ...

  • Page 26

    J3 (x8/x16) 7.2 Write Operations Table 9. Write Operations Versions # Symbol RP# High Recovery to WE# (CE PHWL PHEL (WE#) Low to WE# (CE ELWL WLEL ...

  • Page 27

    Block Erase, Program, and Lock-Bit Configuration Performance Table 10. Configuration Performance # Sym Write Buffer Byte Program Time W16 (Time to Program 32 bytes/16 words) t WHQV3 W16 Byte Program Time (Using Word/Byte Program Command) t EHQV3 Block Program ...

  • Page 28

    J3 (x8/x16) Figure 12. Asynchronous Write Waveform ADDRESS [A] CEx (WE#) [E (W)] W2 WE# (CEx) [W (E)] OE# [G] DATA [D/Q] STS[R] W1 RP# [P] VPEN [V] Figure 13. Asynchronous Write to Read Waveform Address [A] CE# [E] ...

  • Page 29

    Reset Operation Figure 14. AC Waveform for Reset Operation V IH STS ( RP# ( NOTE: STS is shown in its default mode (RY/BY#). Table 11. Reset Specifications # Sym RP# Pulse Low ...

  • Page 30

    J3 (x8/x16) Figure 16. Transient Equivalent Testing Load Circuit NOTE: C Includes Jig Capacitance. L Test Configuration 2.7 V−3.6 V CCQ CC 7.6 Capacitance T = +25 ° MHz A Symbol C ...

  • Page 31

    ... Power and Reset Specifications This section provides an overview of system level considerations for the Intel StrataFlash memory family device. This section provides a brief description of power-up, power-down, decoupling and reset design considerations. 8.1 Power-Up/Down Characteristics In order to prevent any condition that may result in a spurious write or erase operation recommended to power-up and power-down VCC and VCCQ together ...

  • Page 32

    ... The CUI does not occupy an addressable memory location; it’s the mechanism through which the flash device is controlled. 9.1 Bus Operations Overview The local CPU reads and writes flash memory in-system. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles. Table 12. Bus Operations Mode ...

  • Page 33

    ... Bus Read Operation To perform a bus read operation, CEx (refer to CEx is the device-select control; when active, it enables the flash memory device. OE# is the data- output control; when active, the addressed flash memory data is driven onto the I/O bus. For all read states, WE# and RP# must be de-asserted. See Refer to Section 10.0, “ ...

  • Page 34

    ... If a CPU reset occurs with no flash memory reset, proper initialization may not occur because the flash memory may be providing status information instead of array data. Intel StrataFlash memory family devices allow proper initialization following a system reset through the use of the RP# input ...

  • Page 35

    Device Commands voltage ≤ V When the V PEN codes, or blocks are enabled. Placing V and lock-bit configuration operations. Device operations are selected by writing specific commands into the CUI. commands. Table 14. Command Bus-Cycle Definitions (Sheet 1 ...

  • Page 36

    ... Commands other than those shown above are reserved by Intel for future device implementations and should not be used. 2. The Basic Command Set (BCS) is the same as the 28F008SA Command Set or Intel Standard Command Set. The Scalable Command Set (SCS) is also referred to as the Intel Extended Command Set. ...

  • Page 37

    Read Operations The device supports four types of read modes: Read Array, Read Identifier, Read Status, and CFI query. Upon power-up or return from reset, the device defaults to read array mode. To change the device’s read mode, the ...

  • Page 38

    ... To perform a page mode read after any other operation, the Read Array command must be issued to read from the flash array. Asynchronous page mode reads are permitted in all blocks and are used to access register information. During register access, only one word is loaded into the page buffer. ...

  • Page 39

    Read Identifier Codes The Read identifier codes operation outputs the manufacturer code, device-code, and the block lock configuration codes for each block (See details on issuing the Read Device Identifier command). Page-mode reads are not supported in this read ...

  • Page 40

    J3 (x8/x16) Table 18. Status Register Definitions WSMS ESS ECLBS bit 7 bit 6 bit 5 High Z When Status Register Bits Busy? SR.7 = WRITE STATE MACHINE STATUS Ready 0 = Busy Yes SR.6 = ...

  • Page 41

    ... The query register contains an assortment of flash product information such as block size, density, allowable command sets, electrical specifications and other product information. The data contained in this register conforms to the Common Flash Interface (CFI) protocol. To obtain any information from the query register, execute the Read Query Register command. See “ ...

  • Page 42

    ... Write to Buffer To program the flash device, a Write to Buffer command sequence is initiated. A variable number of bytes the buffer size, can be loaded into the buffer and written to the flash device. First, the Write to Buffer Setup command is issued along with the Block Address (see Buffer Flowchart” on page information is loaded and XSR.7 reverts to “ ...

  • Page 43

    ... After the final buffer data is given, a Write Confirm command is issued. This initiates the WSM (Write State Machine) to begin copying the buffer data to the flash array command other than Write Confirm is written to the device, an “Invalid Command/Sequence” error will be generated and SR.5 and SR.4 will be set. For additional buffer writes, issue another Write to Buffer Setup command and check XSR ...

  • Page 44

    ... Erase Operations Flash erasing is performed on a block basis; therefore, only one block can be erased at a time. Once a block is erased, all bits within that block will read as a logic level one. To determine the status of a block erase, poll the Status Register and analyze the bits. This following section describes block erase operations in detail ...

  • Page 45

    ... The only other valid commands while block erase is suspended are Read Query, Read Status Register, Clear Status Register, Configure, and Block Erase Resume. After a Block Erase Resume command is written to the flash memory, the WSM will continue the block erase process. SR.6 and SR.7 will automatically clear and STS (in default mode) will return to V Resume command is written, the device automatically outputs SRD when read (see “ ...

  • Page 46

    ... VPEN allow the user to implement various levels of data protection. The following section describes security features in detail. Other security features are available that are not described in this datasheet. Please contact your local Intel Field Representative for more information. 13.1 Set Block Lock-Bit A flexible block locking scheme is enabled via block lock-bits ...

  • Page 47

    ... Locking the Protection Register The user-programmable segment of the Protection Register is lockable by programming Bit 1 of the PLR to 0. Bit 0 of this location is programmed the Intel factory to protect the unique device number. Bit 1 is set using the Protection Program command to program “0xFFFD” to the PLR ...

  • Page 48

    J3 (x8/x16) Figure 17. Protection Register Memory Map NOTE not used in x16 mode when accessing the Protection Register map (See addressing). For x8 mode A0 is used (See Table 20. Word-Wide Protection Register Addressing Word Use ...

  • Page 49

    Table 21. Byte-Wide Protection Register Addressing (Sheet Factory 7 Factory 8 User 9 User A User B User C User D User E User F User NOTE: All address lines not specified in the above table ...

  • Page 50

    ... Used to control HOLD to a memory controller to prevent accessing a flash memory subsystem while any flash device's WSM is busy. Used to generate a system interrupt pulse when any flash device in an array has completed a block erase. Helpful for reformatting blocks after file system free space reclamation or “cleanup.” ...

  • Page 51

    ... Reserved Used to generate a system interrupt pulse when any flash device in an array has completed a program operation. Provides highest performance for servicing continuous buffer write operations. Used to generate system interrupts to trigger servicing of flash arrays when either erase or program operations are completed, when a common interrupt service routine is desired ...

  • Page 52

    ... Query command. System software should parse this structure to gain critical information such as block size, density, x8/x16, and electrical specifications. Once this information has been obtained, the software will know which command sets to use to enable flash writes, block erases, and otherwise control the flash component. The Query command is part of an overall specification for multiple command set and control interface descriptions called Common Flash Interface, or CFI ...

  • Page 53

    ... The Query command causes the flash component to display the Common Flash Interface (CFI) Query structure or “database.” The structure sub-sections and address locations are summarized below. See AP-646 Common Flash Interface (CFI) and Command Sets (order number 292204) for a full description of CFI commands. ...

  • Page 54

    ... BA = Block Address beginning location (i.e., 02000h is block 2’s beginning location when the block size is 128 Kbyte). 3. Offset 15 defines “P” which points to the Primary Intel-Specific Extended Query Table. A.3 Block Status Register The block status register indicates whether an erase operation completed successfully or whether a given block is locked or can be accessed for flash program/erase operations ...

  • Page 55

    ... A.6 Device Geometry Definition This field provides critical details of the flash device geometry. Table 29. Device Geometry Definition (Sheet Offset Length 27h 1 “n” such that device size = 2 ...

  • Page 56

    ... A.7 Primary-Vendor Specific Extended Query Table Certain flash features and commands are optional. The Primary Vendor-Specific Extended Query table specifies this and other similar information. Table 30. Primary Vendor-Specific Extended Query (Sheet (1) Offset Length P = 31h (P+0)h 3 (P+1)h (P+2)h ...

  • Page 57

    ... Future devices may not support the described “Legacy Lock/Unlock” function. Thus bit 3 would have a value of “0.” Datasheet Description (Optional Flash Features and Commands) Optional feature and command support (1=yes, 0=no) bits 9–31 are reserved; undefined bits are “0.” If bit 31 is “1” then another 31 bit field of optional features follows at the end of the bit-30 field ...

  • Page 58

    ... Description (Optional Flash Features and Commands) Page Mode Read capability bits 0–7 = “n” such that 2 n HEX value represents the number of read-page bytes. See offset 28h for device word width to determine page-mode data output width ...

  • Page 59

    Appendix B Flow Charts Figure 18. Write to Buffer Flowchart Datasheet Start Setup - Write 0xE8 - Block Address Check Buffer Status - Perform read operation - Read Ready Status on signal SR7 No SR7 = 1? Yes Word Count ...

  • Page 60

    J3 (x8/x16) Figure 19. Status Register Flowchart Start Command Cycle - Issue Status Register Command - Address = any dev ice address - Data = 0x70 Data Cycle - Read Status Register SR[7:0] SR7 = ' ...

  • Page 61

    Figure 20. Byte/Word Program Flowchart Start Write 40H, Address Write Data and Address Read Status Register SR Full Status Check if Desired Byte/Word Program Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) SR ...

  • Page 62

    J3 (x8/x16) Figure 21. Program Suspend/Resume Flowchart Start Write B0H Read Status Register SR SR Write FFH Read Data Array Done Reading Yes Write D0H Programming Resumed 62 Bus Operation Write Read Standby Standby 0 ...

  • Page 63

    ... Command 20H, Block Address Write Confirm D0H Block Address Read Status Register SR Full Status Check if Desired Erase Flash Block(s) Complete Datasheet Bus Operation Write Write (Note 1) Read Standby 1. The Erase Confirm byte must follow Erase Setup. This device does not support erase queuing. Please see Application note AP-646 For software erase queuing compatibility ...

  • Page 64

    J3 (x8/x16) Figure 23. Block Erase Suspend/Resume Flowchart Start Write B0H Read Status Register SR.7 = SR.6 = Read Read or Program? Read Array Data Done? Write D0H Block Erase Resumed 64 Operation Standby Standby Block ...

  • Page 65

    Figure 24. Set Block Lock-Bit Flowchart Start Write 60H, Block Address Write 01H, Block Address Read Status Register SR Full Status Check if Desired Set Lock-Bit Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) SR.3 ...

  • Page 66

    J3 (x8/x16) Figure 25. Clear Lock-Bit Flowchart Start Write 60H Write D0H Read Status Register SR Full Status Check if Desired Clear Block Lock-Bits Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) SR.3 = ...

  • Page 67

    Figure 26. Protection Register Programming Flowchart Start Write C0H (Protection Reg. Program Setup) Write Protect. Register Address/Data Read Status Register SR Yes Full Status Check if Desired Program Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See ...

  • Page 68

    ... J3 (x8/x16) Appendix C Design Considerations C.1 Three-Line Output Control The device will often be used in large memory arrays. Intel provides five control inputs (CE0, CE1, CE2, OE#, and RP#) to accommodate multiple memory connections. This control provides for: a. Lowest possible memory power dissipation. b. Complete assurance that data bus contention will not occur. ...

  • Page 69

    ... Power Dissipation When designing portable systems, designers must consider battery power consumption not only during device operation, but also for data retention during system idle time. Flash memory’s nonvolatility increases usable battery life because data is retained when system power is removed. ...

  • Page 70

    ... Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should contact their local Intel or distribution sales office. 2. Visit Intel’s World Wide Web home page at http://www.intel.com for technical documentation and tools. 3. For the most current information on Intel StrataFlash memory, visit our website at http:// developer.intel.com/design/flash/isf. 70 ...

  • Page 71

    ... PC28F256J3C125 PC28F128J3C120 PC28F640J3C115 PC28F320J3C110 256-Mbit J3 (x8/x16) 5 Access Speed (ns) 1 256 Mbit = 125 128 Mbit = 150, 120 64 Mbit = 120, 115 32 Mbit = 110 ® Intel 0.25 micron lithography C = Intel® 0.18 micron lithography Voltage ( PEN V/3 V Product Family ® Intel StrataFlash memory, 2 bits-per-cell 71 ...

  • Page 72

    J3 (x8/x16) 72 Datasheet ...