K6T1008C2E-GB70

Manufacturer Part NumberK6T1008C2E-GB70
ManufacturerSamsung Semiconductor
K6T1008C2E-GB70 datasheet
 


Specifications of K6T1008C2E-GB70

Density1MbAccess Time (max)70ns
Sync/asyncAsynchronousArchitectureNot Required
Clock Freq (max)Not RequiredMHzOperating Supply Voltage (typ)5V
Address Bus17bPackage TypeSOP
Operating Temp Range0C to 70CNumber Of Ports1
Supply Current50mAOperating Supply Voltage (min)4.5V
Operating Supply Voltage (max)5.5VOperating Temperature ClassificationCommercial
MountingSurface MountPin Count32
Word Size8bNumber Of Words128K
Lead Free Status / Rohs StatusNot Compliant  
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K6T1008C2E Family
Document Title
128Kx8 bit Low Power CMOS Static RAM
Revision History
Revision No.
History
0.0
Design target
1.0
Finalize
- Improve t
form 55ns to 50ns for 70ns product.
WP
- Remove 55ns speed bin from industrial product.
1.01
Errata correction
2.0
Revise
3.0
Revise
- Add 55ns parts to industrial products.
4.0
Revise
- Add automotive temperature products
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserves the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions. If you have any questions, please contact the SAMSUNG branch offices.
CMOS SRAM
Draft Data
October 12, 1998
August 30, 1999
December 1, 1999
February 14, 2000
March 3, 2000
May 30, 2002
1
Remark
Preliminary
Final
Final
Final
Final
Revision 4.0
May 2002

K6T1008C2E-GB70 Summary of contents

  • Page 1

    ... K6T1008C2E Family Document Title 128Kx8 bit Low Power CMOS Static RAM Revision History Revision No. History 0.0 Design target 1.0 Finalize - Improve t form 55ns to 50ns for 70ns product Remove 55ns speed bin from industrial product. 1.01 Errata correction 2.0 Revise 3.0 Revise - Add 55ns parts to industrial products ...

  • Page 2

    ... No Connection SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. GENERAL DESCRIPTION The K6T1008C2E families are fabricated by SAMSUNG s advanced CMOS process technology. The families support various operating temperature ranges and have various pack- age types for user flexibility of system design. The families also support low data retention voltage for battery back-up operation with low data retention current ...

  • Page 3

    ... K6T1008C2E-DB55 32-DIP, 55ns, LL Pwr K6T1008C2E-DB70 32-DIP, 70ns, LL Pwr K6T1008C2E-GL55 32-SOP, 55ns, L Pwr K6T1008C2E-GL70 32-SOP, 70ns, L Pwr K6T1008C2E-GB55 32-SOP, 55ns, LL Pwr K6T1008C2E-GB70 32-SOP, 70ns, LL Pwr K6T1008C2E-TB55 32-TSOP-F, 55ns, LL Pwr K6T1008C2E-TB70 32-TSOP-F, 70ns, LL Pwr K6T1008C2E-RB55 32-TSOP-R, 55ns, LL Pwr K6T1008C2E-RB70 32-TSOP-R, 70ns, LL Pwr FUNCTIONAL DESCRIPTION ...

  • Page 4

    ... Output low voltage V OL Output high voltage V OH Standby Current(TTL Standby Current(CMOS) I SB1 for Low power product, in case of Low Low power products are comercial=10 A, industrial= Product K6T1008C2E Family All Family K6T1008C2E Family K6T1008C2E Family Symbol Test Condition Test Conditions V =Vss to Vcc IN CS ...

  • Page 5

    ... K6T1008C2E Family AC OPERATING CONDITIONS TEST CONDITIONS ( Test Load and Input/Output Reference) Input pulse level: 0.8 to 2.4V Input rising and falling time: 5ns Input and output reference voltage:1.5V Output load(see right): C =100pF+1TTL L C =50pF+1TTL L AC CHARACTERISTICS (V =4.5~5.5V, Commercial Product Industrial Product Parameter List ...

  • Page 6

    ... K6T1008C2E Family TIMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) Address Data Out Previous Data Valid TIMING WAVEFORM OF READ CYCLE(2) Address High-Z Data out NOTES (READ CYCLE and are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage ...

  • Page 7

    ... K6T1008C2E Family TIMING WAVEFORM OF WRITE CYCLE(1) Address Data in Data Undefined Data out TIMING WAVEFORM OF WRITE CYCLE(2) Address Data in Data out (WE Controlled CW( CW(2) t WP(1) t AS( Data Valid t WHZ (CS Controlled CW(2) AS( WP( Data Valid High-Z 7 CMOS SRAM t WR( WR( High-Z Revision 4.0 May 2002 ...

  • Page 8

    ... K6T1008C2E Family TIMING WAVEFORM OF WRITE CYCLE(3) Address Data in Data out NOTES (WRITE CYCLE write occurs during the overlap of a low CS CS going high and WE going low: A write end at the earliest transition among measured from the begining of write to the end of write measured from the CS ...

  • Page 9

    ... K6T1008C2E Family PACKAGE DIMENSIONS 32 DUAL INLINE PACKAGE (600mil) #32 13.60 0.20 0.535 0.008 #1 1. 0.075 32 PLASTIC SMALL OUTLINE PACKAGE (525mil) #32 #1 20.87 0.822 20.47 0.806 +0.100 0.41 -0.050 0. +0.004 0.016 0.028 -0.002 42.31 MAX 1.666 41.91 0.20 1.650 0.008 0.46 0.10 0.018 ...

  • Page 10

    ... K6T1008C2E Family PACKAGE DIMENSIONS 32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0820F) +0.10 0.20 -0.05 +0.004 0.008 -0.002 #1 0.50 0.0197 #16 0.25 TYP 0.010 0~8 0.45 ~0.75 0.018 ~0.030 32 THIN SMALL OUTLINE PACKAGE TYPE I (0820R) +0.10 0.20 -0.05 +0.004 0.008 -0.002 #16 0.50 0.0197 #1 0 ...