JS28F320C3BD70 Micron Technology Inc, JS28F320C3BD70 Datasheet - Page 39

• Manufacturer Part Number: JS28F320C3BD70
• Manufacturer: Micron Technology Inc

Specifications of JS28F320C3BD70

• Density: 32Mb
• Access Time (max): 70ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 21b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 16b
• Number Of Words: 2M
• Supply Current: 18mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Compliant

C3 Discrete
9.0
9.1
Table 21: Bus Operations
9.1.1
9.1.2
9.1.3
9.1.4
March 2008
290645-24
Read
Write
Output Disable
Standby
Reset
Note:
X = Don’t Care (V
Mode
Device Operations
The C3 Discrete device uses a CUI and automated algorithms to simplify Program and
Erase operations. The CUI allows for 100% CMOS-level control inputs and fixed power
supplies during erasure and programming.
The internal WSM completely automates Program and Erase operations while the CUI
signals the start of an operation and the Status Register reports device status. The CUI
handles the WE# interface to the data and address latches as well as system status
requests during WSM operation.
Bus Operations
The C3 Discrete device performs read, program, and erase operations in-system
through the local CPU or microcontroller. Four control pins (CE#, OE#, WE#, and RP#)
manage the data flow in and out of the flash device.
these bus operations.
Read
When performing a read cycle, CE# and OE# must be asserted; WE# and RP# must be
deasserted. CE# is the device selection control; when active low, it enables the flash
memory device. OE# is the data output control; when low, data is output on DQ[15:0].
See
Write
A write cycle occurs when both CE# and WE# are low; RP# and OE# are high.
Commands are issued to the Command User Interface (CUI). The CUI does not occupy
an addressable memory location. Address and data are latched on the rising edge of
the WE# or CE# pulse, whichever occurs first. See
Waveform” on page
Output Disable
With OE# at a logic-high level (V
placed in a high-impedance state.
Standby
Deselecting the device by bringing CE# to a logic-high level (V
standby mode, which substantially reduces device power consumption without any
latency for subsequent read accesses. In standby, outputs are placed in a high-
Figure 9, “Read Operation Waveform” on page
IL
or V
IH
)
33.
RP#
V
V
V
V
V
IH
IH
IH
IH
IL
IH
), the device outputs are disabled. DQ[15:0] are
CE#
V
V
V
V
X
IH
IL
IL
IL
OE#
V
V
V
X
X
IH
IH
IL
29.
Figure 10, “Write Operations
Table 21 on page 39
IH
WE#
V
V
V
X
X
) places the device in
IH
IH
IL
summarizes
DQ[15:0]
High-Z
High-Z
High-Z
D
D
OUT
IN
Datasheet
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