JS28F320C3BD70 Micron Technology Inc, JS28F320C3BD70 Datasheet - Page 50

• Manufacturer Part Number: JS28F320C3BD70
• Manufacturer: Micron Technology Inc

Specifications of JS28F320C3BD70

• Density: 32Mb
• Access Time (max): 70ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 21b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 16b
• Number Of Words: 2M
• Supply Current: 18mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Compliant

11.4
11.5
11.5.1
Datasheet
50
To change block locking during an Erase operation, first issue the Erase Suspend
command (0xB0), and then check the Status Register until it indicates that the Erase
operation has been suspended. Next, write the preferred Lock command sequence to a
block and the Lock status will be changed. After completing any preferred Lock, Read,
or Program operations, resume the Erase operation with the Erase Resume command
(0xD0).
If a block is Locked or Locked Down during a Suspended Erase of the same block, the
locking status bits will be changed immediately. But when the Erase is resumed, the
Erase operation will complete.
Locking operations cannot be performed during a Program Suspend. Refer to
A, “Write State Machine States” on page 53
commands are valid during Erase Suspend.
Status Register Error Checking
Using nested-locking or program-command sequences during Erase Suspend can
introduce ambiguity into Status Register results.
Since locking changes are performed using a two-cycle command sequence, for
example, 0x60 followed by 0x01 to lock a block. Following the Block Lock, Block
Unlock, or Block Lock-Down Setup command (0x60) with an invalid command will
produce a Lock-Command error (SR[4] and SR[5] will be set to 1) in the Status
Register. If a Lock-Command error occurs during an Erase Suspend, SR[4] and SR[5]
will be set to 1 and will remain at 1 after the Erase is resumed. When Erase is
complete, any possible error during the Erase cannot be detected by the Status
Register because of the previous Lock-Command error.
A similar situation happens if an error occurs during a Program-Operation error nested
within an Erase Suspend.
128-Bit Protection Register
The C3 device architecture includes a 128-bit protection register than can be used to
increase the security of a system design. For example, the number contained in the
protection register can be used to “match” the flash component with other system
components, such as the CPU or ASIC, preventing device substitution. Application note,
AP-657 Designing with the Advanced+ Boot Block Flash Memory Architecture, contains
additional application information.
The 128 bits of the protection register are divided into two 64-bit segments. One of the
segments is programmed at the Numonyx factory with a unique 64-bit number, which
is unchangeable. The other segment is left blank for customer designs to program, as
preferred. Once the customer segment is programmed, it can be locked to prevent
further programming.
Reading the Protection Register
The protection register is read in the Read-Identifier mode. The device is switched to
this mode by issuing the Read Identifier command (0x90). Once in this mode, read
cycles from addresses shown in
specified information. To return to Read-Array mode, issue the Read Array command
(0xFF).
Figure 15, “Protection Register
for detailed information on which
Mapping” retrieve the
C3 Discrete
Appendix
March 2008
290645-24