DSPA56371AF150B Freescale Semiconductor, DSPA56371AF150B Datasheet - Page 25

• Manufacturer Part Number: DSPA56371AF150B
• Manufacturer: Freescale Semiconductor

Specifications of DSPA56371AF150B

• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 150MHz
• Mips: 150
• Device Input Clock Speed: 150MHz
• Program Memory Size: 192KB
• Operating Supply Voltage (typ): 1.25/3.3V
• Operating Supply Voltage (min): 1.2/3.14V
• Operating Temp Range: -40C to 115C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: LQFP
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor
Signal Name
FSR_1
FST_1
PE1
PE4
Input, output, or
Input, output, or
Input or output
Input or output
disconnected
disconnected
Signal Type
Table 9. Enhanced Serial Audio Interface_1 Signals
State during
disconnected
disconnected
Reset
GPIO
GPIO
DSP56371 Data Sheet, Rev. 4.1
Frame Sync for Receiver_1—This is the receiver frame sync
input/output signal. In the asynchronous mode (SYN=0), the
FSR_1 pin operates as the frame sync input or output used by all
the enabled receivers. In the synchronous mode (SYN=1), it
operates as either the serial flag 1 pin (TEBE=0), or as the
transmitter external buffer enable control (TEBE=1, RFSD=1).
When this pin is configured as serial flag pin, its direction is
determined by the RFSD bit in the RCCR_1 register. When
configured as the output flag OF1, this pin will reflect the value of
the OF1 bit in the SAICR_1 register, and the data in the OF1 bit
will show up at the pin synchronized to the frame sync in normal
mode or the slot in network mode. When configured as the input
flag IF1, the data value at the pin will be stored in the IF1 bit in the
SAISR register, synchronized by the frame sync in normal mode
or the slot in network mode.
Port E1—When the ESAI_1 is configured as GPIO, this signal is
individually programmable as input, output, or internally
disconnected.
The default state after reset is GPIO disconnected.
Internal Pull down resistor.
This input is 5 V tolerant.
Frame Sync for Transmitter_1—This is the transmitter frame
sync input/output signal. For synchronous mode, this signal is the
frame sync for both transmitters and receivers. For asynchronous
mode, FST_1 is the frame sync for the transmitters only. The
direction is determined by the transmitter frame sync direction
(TFSD) bit in the ESAI_1 transmit clock control register
(TCCR_1).
Port E4—When the ESAI_1 is configured as GPIO, this signal is
individually programmable as input, output, or internally
disconnected.
The default state after reset is GPIO disconnected.
Internal Pull down resistor.
This input is 5 V tolerant.
Signal Description
Signal/Connection Descriptions
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