DSPA56371AF150B Freescale Semiconductor, DSPA56371AF150B Datasheet - Page 8

• Manufacturer Part Number: DSPA56371AF150B
• Manufacturer: Freescale Semiconductor

Specifications of DSPA56371AF150B

• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 150MHz
• Mips: 150
• Device Input Clock Speed: 150MHz
• Program Memory Size: 192KB
• Operating Supply Voltage (typ): 1.25/3.3V
• Operating Supply Voltage (min): 1.2/3.14V
• Operating Temp Range: -40C to 115C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: LQFP
• Lead Free Status / Rohs Status: Compliant

DSP56371 Overview
2.4.6
The clock generator in the DSP56300 core is composed of two main blocks: the PLL, which performs
clock input division, frequency multiplication, skew elimination and the clock generator (CLKGEN),
which performs low-power division and clock pulse generation. PLL-based clocking:
The PLL allows the processor to operate at a high internal clock frequency using a low frequency clock
input. This feature offers two immediate benefits:
2.4.7
The memory space of the DSP56300 core is partitioned into program memory space, X data memory space
and Y data memory space. The data memory space is divided into X and Y data memory in order to work
with the two Address ALUs and to feed two operands simultaneously to the Data ALU. Memory space
includes internal RAM and ROM and can not be expanded off-chip.
There is an instruction patch module. The patch module is used to patch program ROM. The memory
switch mode is used to increase the size of program RAM as needed (switch from X data RAM and/or Y
data RAM).
There are on-chip ROMs for program and bootstrap memory (64K x 24-bit), X ROM (32K x 24-bit) and
Y ROM (32K x 24-bit).
More information on the internal memory is provided in the
2.4.8
Memory cannot be expanded off-chip. There is no external memory bus.
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Triggering from interrupt lines and all peripherals
Allows change of low-power divide factor (DF) without loss of lock
Provides output clock with skew elimination
Provides a wide range of frequency multiplications (1 to 255), predivider factors (1 to 31), PLL
feedback multiplier (2 or 4), output divide factor (1, 2 or 4), and a power-saving clock divider
(2
A lower frequency clock input reduces the overall electromagnetic interference generated by a
system.
The ability to oscillate at different frequencies reduces costs by eliminating the need to add
additional oscillators to a system.
The PLL will momentarily overshoot the target frequency when the PLL is first enabled or
when the VCO frequency is modified. It is important that when modifying the PLL
frequency or enabling the PLL that the two-step procedure defined in
Overview
i
: i = 0 to 7) to reduce clock noise
PLL-based Clock Oscillator
On-Chip Memory
Off-Chip Memory Expansion
be followed.
DSP56371 Data Sheet, Rev. 4.1
NOTE
DSP56371 User’s Manual, Memory
Section 3, DSP56371
Freescale Semiconductor
section.