DSPA56371AF150B Freescale Semiconductor, DSPA56371AF150B Datasheet - Page 39

• Manufacturer Part Number: DSPA56371AF150B
• Manufacturer: Freescale Semiconductor

Specifications of DSPA56371AF150B

• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 150MHz
• Mips: 150
• Device Input Clock Speed: 150MHz
• Program Memory Size: 192KB
• Operating Supply Voltage (typ): 1.25/3.3V
• Operating Supply Voltage (min): 1.2/3.14V
• Operating Temp Range: -40C to 115C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: LQFP
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor
Note:
No.
18
19
20
21
22
1. When using fast interrupts and IRQA, IRQB, IRQC, and IRQD are defined as level-sensitive, timings 19 through 21 apply
2. For PLL disable, using external clock (PCTL Bit 13 = 0), no stabilization delay is required and recovery time will be
3. Periodically sampled and not 100% tested
4. RESET duration is measured during the time in which RESET is asserted, V
Delay from interrupt trigger to interrupt code
execution.
Duration of level sensitive IRQA assertion to
ensure interrupt service (when exiting Stop)
Interrupt Requests Rate
DMA Requests Rate
• PLL is active during Stop and Stop delay is
• PLL is active during Stop and Stop delay is not
• PLL is not active during Stop and Stop delay is
• PLL is not active during Stop and Stop delay is
• Delay from IRQA, IRQB, IRQC, IRQD, NMI
• ESAI, ESAI_1, SHI, DAX, Timer
• DMA
• IRQ, NMI (edge trigger)
• IRQ (level trigger)
• Data read from ESAI, ESAI_1, SHI, DAX
• Data write to ESAI, ESAI_1, SHI, DAX
• Timer
• IRQ, NMI (edge trigger)
to prevent multiple interrupt service. To avoid these timing restrictions, the deasserted Edge-triggered mode is
recommended when using fast interrupts. Long interrupts are recommended when using Level-sensitive mode.
defined by the OMR Bit 6 settings.
For PLL enable, (if bit 12 of the PCTL register is 0), the PLL is shutdown during Stop. Recovering from Stop requires the
PLL to get locked. The PLL lock procedure duration, PLL Lock Cycles (PLC), may be in the range of 0.5 ms.
valid. When the V
met, the device circuitry will be in an uninitialized state that can result in significant power consumption and heat-up.
Designs should minimize this state to the shortest possible duration.
enabled
(OMR Bit 6 = 0)
enabled
(OMR Bit 6 = 1)
enabled (OMR Bit 6 = 0)
not enabled (OMR Bit 6 = 1)
assertion to general-purpose transfer output
valid caused by first interrupt instruction
execution
Table 19. Reset, Stop, Mode Select, and Interrupt Timing (continued)
Characteristics
DD
is valid, but the other “required RESET duration” conditions (as specified above) have not been yet
DSP56371 Data Sheet, Rev. 4.1
2, 3
9+(128KxT
(25 x T
9+(128K× T
10 x T
Expression
10 xT
12 c T
12 x T
25× T
8 x T
8 x T
6 x T
7 x T
2 x T
3 x T
Reset, Stop, Mode Select, and Interrupt Timing
C
C
C
)+T
+ 3.0
C
C
C
C
C
C
C
+ 5
C
C
C
)+T
DD
lock
C)
lock
is valid, and the EXTAL input is active and
60.0
Min
704
138
5.7
—
—
—
—
—
—
—
—
5
Max
59.0
—
—
—
—
—
—
—
—
—
—
Unit
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
ns
39