H5PS1G83EFR-S6C HYNIX SEMICONDUCTOR, H5PS1G83EFR-S6C Datasheet - Page 35

• Manufacturer Part Number: H5PS1G83EFR-S6C
• Description: 58T1895
• Manufacturer: HYNIX SEMICONDUCTOR

Specifications of H5PS1G83EFR-S6C

• Memory Type: SDRAM
• Memory Configuration: 128M X 8
• Access Time: 15ns
• Memory Case Style: FBGA
• No. Of Pins: 60
• Operating Temperature Range: 0°C To +85°C
• Memory Size: 1 Gbit
• Rohs Compliant: Yes

Rev. 0.4 / Nov 2008
1) For all input signals the total tIS(setup time) and tIH(hold) time) required is calculated by adding the
datasheet value to the derating value listed in above Table.
Setup(tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of
V
the slew rate between the last crossing of V
always earlier than the nominal slew rate for line between shaded ‘V
rate for derating value(see fig a.) If the actual signal is later than the nominal slew rate line anywhere
between shaded ‘V
to dc level is used for derating value(see Fig b.)
Hold(tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of
VIL(dc)max and the first crossing of V
slew rate between the last crossing of V
line between shaded ‘dc to V
signal is earlier than the nominal slew rate line anywhere between shaded ‘dc to V
rate of a tangent line to the actual signal from the dc level to V
d.)
Although for slow rates the total setup time might be negative(i.e. a valid input signal will not have reached
V
tion and reach V
For slew rates in between the values listed in table, the derating values may obtained by linear interpolation.
These values are typically not subject to production test. They are verified by design and characterization.
REF
IH/IL
(dc) and the first crossing of V
(ac) at the time of the rising clock transition) a valid input signal is still required to complete the transi-
Command /
rate(V/ns)
Address
Slew
IH/IL
REF
0.25
0.15
(ac).
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
(dc) to ac region’, the slew rate of a tangent line to the actual signal from the ac level
△ tIS
-1000
+143
+133
+120
+100
-100
-168
-200
-325
-517
+15
+67
-13
-22
-34
-60
REF
-5
0
2.0 V/ns
tIS, tIH Derating Values for DDR2-667, DDR2-800
(dc) region’, use nominal slew rate for derating value(see Fig.c) If the actual
IH
(ac)min. Setup(tIS) nominal slew rate for a falling signal is defined as
△ tIH
-1125
REF
-125
-188
-292
-375
-500
-708
+94
+89
+83
+75
+45
+21
-14
-31
-54
-83
0
REF
CK, CK Differential Slew Rate
(dc). Hold(tIH) nominal slew rate for a falling signal is defined as the
(dc). If the actual signal is always later than the nominal slew rate
REF
(dc) and the first crossing of V
△ tIS
+180
+173
+163
+150
+130
-138
-170
-395
-487
-970
+97
+30
+25
+17
-30
-70
+8
-4
1.5 V/ns
△ tIH
-1095
+124
+119
+113
+105
-158
-262
-345
-470
-678
+51
+30
+16
+75
-24
-53
-95
-1
REF
(dc) level is used for derating value(see Fig
△ tIS
+210
+203
+193
+180
+150
+127
-108
-140
-265
-457
-940
+60
+55
+47
+38
+26
-40
0
REF
1.0 V/ns
(dc) to ac region’, use nominal slew
-1065
△ tIH
+154
+149
+143
+135
+105
-128
-232
-315
-440
-648
+81
+60
+46
+29
-23
-65
IL
+6
(ac)max. If the actual signal is
REF
Uni ts
(dc) region’, the slew
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
H5PS1G43EFR
H5PS1G83EFR
H5PS1G63EFR
Note s
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
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