TDA9110 STMicroelectronics, TDA9110 Datasheet

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TDA9110

Manufacturer Part Number
TDA9110
Description
Deflection Processor 32-Pin SPDIP
Manufacturer
STMicroelectronics
Datasheet

Specifications of TDA9110

Package
32SPDIP
Operating Temperature
0 to 70 °C

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HORIZONTAL
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VERTICAL
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GENERAL
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DESCRIPTION
The TDA9110 is a monolithic integrated circuit as-
sembled in 32-pin shrunk dual in line plastic pack-
age. This IC controls all the functions related to the
horizontal and vertical deflection in multimode or
multi-frequency computer display monitors.
The internal synchro processor, combined with the
very powerful geometry correction block make the
TDA9110 suitable for very high performance moni-
tors with very few external components.
The horizontal jitter level is extremely low. (Typical
standard deviation : 300ps @ 31kHz).
It is particularly well suited for high-end 15” and 17”
monitors.
December 1997
This is advance information on a new product now in development or undergoing evaluatio n. Details are subject to change without notice.
2
C GEOMETRY CORRECTIONS
EXTREMELY LOW JITTER LEVEL
SELF-ADAPTATIVE
DUAL PLL CONCEPT
150kHz MAXIMUM FREQUENCY
X-RAY PROTECTION INPUT
I
H-POSITION
VERTICAL RAMP GENERATOR
50 TO 165Hz AGC LOOP
GEOMETRY TRACKING WITH V-POS & AMP
I
V-AMP, V-POS, S-CORR, C-CORR
DC BREATHING COMPENSATION
VERTICAL PARABOLA GENERATOR
(Pincushion, Keystone)
HORIZONTAL SIZE CONTROL (Amplitude)
HORIZONTAL DYNAMIC PHASE
(Side Pin Balance & Parallelogram)
HORIZONTAL AND VERTICAL DYNAMIC FO-
CUS (Horizontal Focus Amplitude, Horizontal
Focus Symmetry, Vertical Focus Amplitude)
SYNCHRO PROCESSOR
12V SUPPLY VOLTAGE
8V REFERENCE VOLTAGE
HOR. & VERT. LOCK UNLOCK OUTPUTS
READ/WRITE I
HORIZONTAL AND VERTICAL MOIRE
2
2
C CONTROLS : HORIZONTAL DUTY-CYCLE,
C CONTROLS :
2
C INTERFACE
LOW-COST DEFLECTION PROCESSOR
FOR MULTISYNC MONITORS
Combined with ST7275 Microcontroller family,
TDA9206 (Video preamplifier) and STV942x
(On-Screen Display controller) the TDA9110
allows to built fully I
display monitors, with a reduce nu mber of ex-
ternal compon ents.
PIN CONNECTIONS
HFOCUSCAP
HLOCKOUT
HLOCKCAP
HVFOCUS
VSYNC-IN
HMOIRE
H/HVIN
PLL2C
PLL1F
HGND
HPOS
HREF
HFLY
FC1
C0
R0
ORDER CODE : TDA9110
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
(Plastic Package)
SHRINK32
2
C bus controlled computer
PRODUCT PREVIEW
TDA9110
32
31
30
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28
27
26
25
24
23
22
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20
19
18
17
5V
SDA
SCL
V
HSIZE
GND
HOUT
XRAY
EWOUT
VOUT
VCAP
V
VAGCCAP
VGND
DCBREATH
GND
CC
REF
1/29

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TDA9110 Summary of contents

Page 1

... READ/WRITE I C INTERFACE HORIZONTAL AND VERTICAL MOIRE DESCRIPTION The TDA9110 is a monolithic integrated circuit as- sembled in 32-pin shrunk dual in line plastic pack- age. This IC controls all the functions related to the horizontal and vertical deflection in multimode or multi-frequency computer display monitors. The internal synchro processor, combined with the ...

Page 2

... TDA9110 PIN CONNECTIONS Pin Name 1 H/HVIN TTL compatible Horizontal Synchro Input 2 VSYNCIN TTL compatible Vertical Synchro Input (for separated H&V) 3 HMOIRE Horizontal Moire Output (to be connected to PLL2C through a resistor divider) 4 HLOCKOUT First PLL Lock/Unlock Output (0V unlocked - 5V locked) 5 PLL2C Second PLL Loop Filter ...

Page 3

... Vertical Moiré Output Controlled V-Moiré Amplitude Frequency Generator for Burn-in 2 Fast I C Read/Write Horizontal Moiré Output controlled H-Moiré Amplitude DC HSize Output Amplitude Control Parameter TDA9110 Value Unit 15 to 150 kHz 1 to 4.5 F0 YES YES YES YES 10 % YES ...

Page 4

... TDA9110 BLOCK DIAGRAM HOUT PLL2C HFLY FC1 C0 R0 HLOCKCAP HLOCKOUT HPOS PLL1F 4/29 EWOUT OUT V DCBREATH AGCCAP V CAP V ...

Page 5

... C) amb Test Conditions Low Level High Level Pins 1, 2 Low level High Level Pin 4, Cout = 20pF Locked Unlocked ) on H 820pF amb Test Conditions Pin 30 Pin 30 Pin 30 Pins 30,31 Pin 31 TDA9110 Value Unit 13.5 V 5.7 V 1.8 V 4.0 V 5.5 V 6 300 V 2 ...

Page 6

... TDA9110 HORIZONTAL SECTION Operating Conditions Symbol Parameter VCO R Minimum Oscillator Resistor 0(Min.) C Minimum Oscillator Capacitor 0(Min.) F Maximum Oscillator Frequency (Max.) OUTPUT SECTION I12m Maximum Input Peak Current HOI Horizontal Drive Output Maximum Current Electrical Characteristics (V = 12V Symbol Parameter SUPPLY AND REFERENCE VOLTAGES ...

Page 7

... Fixed for each frequency (Pin 16 10k , Pin 15 LOAD Sub-Address 03, Pin 15 50kHz, Keystone Typ Sub-Address 04 50kHz, Typ Amp B/A A/B A/B Sub-Address 0F Sub-Address 05 Byte 10000000 Byte 11000000 Byte 11111111 Sub-Address 06 Byte x0000000 Byte x1111111 TDA9110 Typ. Max. Unit 0. ppm 1.6 V 3.7 V 7.5 V ...

Page 8

... TDA9110 VERTICAL SECTION Operating Conditions Symbol Parameter OUTPUTS SECTION VEWM Maximum EW Output Voltage VEWm Minimum EW Output Voltage R Minimum Load for less than 1% Vertical Amplitude Drift LOAD Electrical Characteristics (V = 12V Symbol Parameter VERTICAL RAMP SECTION VRB Voltage at Ramp Bottom Point VRT Voltage at Ramp Top Point (with Synchro) V ...

Page 9

... Byte x1111111 Byte x1000000 Subaddress 05 Byte 10000000 Byte 11000000 Byte 11111111 Subaddress 0E Byte x1111111 Byte x1000000 Subaddress 06 Byte x0000000 Byte x1111111 Subaddress 0C Byte 01x11111 > REF REF REF-V TDA9110 Min. Typ. Max. Unit 2.5 V 100 ppm/C 2 0.45 V 0.8 V 1. 0.52 ...

Page 10

... TDA9110 Figure 1 : Vertical Dynamic Focus Function VDF AMP VDF DC A Figure 3 : Dynamic Horizontal Phase Control Output A SPB PARA 10/29 Figure 2 : E/W Output Figure 4 : Keystone Effect on E/W Output (PCC Inhibited) B DHPC PARA Keyadj ...

Page 11

... TYPICAL VERTICAL OUTPUT WAVEFORMS Sub Function Pin Address Vertical Size 05 23 Vertical Position Control Vertical Linearity Vertical Linearity Byte Specification V OUTDC 2.25V 10000000 V OUTDC 3.75V 11111111 x0000000 3.2V x1000000 3.5V x1111111 3.8V 0xxxxxxx Inhibited V 1x111111 1x000000 1x111111 TDA9110 Picture Image 11/29 ...

Page 12

... TDA9110 GEOMETRY OUTPUT WAVEFORMS Sub Function Pin Address Trapezoid 09 24 Control Pin Cushion 0A 24 Control Parrallelogram 0E Internal Control Parallelogram Side Pin Balance 0D Internal Control Vertical Dynamic 32 Focus with Horizontal 12/29 Byte Specification EWamp Inhibited. 2.5V 0.9V 1X000000 1X111111 2.5V 0.9V Keystone Inhibited 2 ...

Page 13

... Synchro Priority / Horizontal Focus Amplitude Refresh / Horizontal Focus Keystone Vertical Ramp Amplitude Vertical Position Adjustment Correction Correction E/W Keystone E/W Amplitude Horizontal Size Control Vertical Moiré Side Pin Balance Parallelogram Vertical Dynamic Focus Amplitude Synchro and Polarity Detection TDA9110 13/29 ...

Page 14

... TDA9110 BUS ADDRESS TABLE (continued WRITE MODE HDrive 00 0, off [1], on Xray 01 1, reset [1] [0] [0] HMoire [0], off Sync 03 0, Comp [1] [0] [1], Sep Detect 04 Refresh [0], off Vramp 05 0, off [1] [0] [1 [1] [0] S Select [1] [0] C Select [1] [0] EW Key 09 0, off [1] [1] EW Sel 0A 0, off ...

Page 15

... I.6 - Synchro Identification Status The MCU can choose via the I priority thanks to the system identification status provided by the TDA9110. The extracted Vertical synchro pulse is available when this identification status has been received and when the 12V is supplied. Even in Power managementmode the IC is able to inform the MCU that synchrosignals were detected due to its 5V supply ...

Page 16

... TDA9110 OPERATING DESCRIPTION (continued) Of course, when the choice is done, we can refresh the synchro detectionsand verify that the extracted Vsync is present and that no synchro type change have occured. Synchro processor is also giving synchro polarity information. I status TheIC can inform the MCUabout the 1st Horizontal PLL or Vertical section status (locked or not), and about the Xray protection (activated or not) ...

Page 17

... Sawtooth 7/8T H Phase REF1 H Synchro Phase REF1 is obtained by comparison between the sawtooth and a DC voltage adjustable between 2.60V and 3.80V. The PLL1 ensures the exact coincidence between the signals phase REF and HSYNS. A T/10 phase adjustment is possible. TDA9110 PLL1F VCO OSC I ...

Page 18

... From A Phase NOR1 Comparator The TDA9110 also includes a Lock/Unlock identifi- cation block which senses in real time whether the the PLL1 is locked or not on the incominghorizontal synchro signal. The resulting information is avail- able on Hlockout (see Synchro Processor). The block function is described in Figure 12. ...

Page 19

... This protection is reset either (see Figure 16). II.6 - Horizontal and Vertical Dynamic Focus The TDA9110 delivers a horizontalparabola which is added on a vertical parabola waveform on Pin 15. This horizontal parabola comes from a saw- tooth. The phase advance versus Horizontal fly- back middle is kept constant for each frequency (about 860ns) ...

Page 20

... TDA9110 OPERATING DESCRIPTION (continued) Figure 17 Horizontal Flyback Internal Trigged Horizontal Flyback Horizontal Focus Cap Sawtooth Horizontal Dynamic Focus Parabola Output II.7 - Moire Output The moire output is intented to correct a beat between the horizontal video pixel period and the current CRT pixel width. ...

Page 21

... The dynamic Horizontalphasecontrol current drives internally the H-position, moving the Hfly position on the Horizontal sawtooth in the range of both on SidePin Balance and Parallelogram. AMP EW amp VDCIN Keystone Sidepin amp VDCOUT Parallelogram TDA9110 - V ) OUT DCOUT 2 C select bit. 1. Internal Vertical Dynamic Focus added to ...

Page 22

... TDA9110 OPERATING DESCRIPTION (continued) Figure 21 : Vertical Part Block Diagram 2 SYNCHRO OSCILLATOR V_SYNC POLARITY PARABOLA GENERATOR III EWOUT = 2. OUT DCOUT + OUT DCOUT K1 is adjustable by the EW amplitude adjustable by the Keystone I C register III HSize Output Control A 7 bits D/A converter is available on Pin 28. The ...

Page 23

... DCOUT with VPOS equals -1 for minimum vertical position register value and +1 for maximum The current available on Pin regis OSC 8 with C : capacitor connected on Pin 22 OSC f : synchronization frequency TDA9110 ) to OUT 2 C 300mV. can be modu- DCOUT - 0. MID AMP ; typically 3.5V, the middle + 0.3 (VPOS) ...

Page 24

... TDA9110 INTERNAL SCHEMATICS Figure 22 5V 200 Pins 1 -2 H/HVIN VSYNC-IN Figure HLOCKOUT Figure 26 HREF 12V 24/29 Figure 23 5V HMOIRE 3 Figure 25 12V HREF 13 PLL2C 5 Figure 27 12V HREF ...

Page 25

... INTERNAL SCHEMATICS (continued) Figure 28 HREF HREF 13 13 12V R0 8 Figure 30 12V HPOS 10 Figure 32 12V HLOCKCAP 14 HREF 13 Figure 29 PLL1F 9 Figure 31 12V HFLY 12 Figure 33 HREF 13 12V HFOCUS 15 TDA9110 HREF 13 12V 25/29 ...

Page 26

... TDA9110 INTERNAL SCHEMATICS (continued) Figure 34 HREF 13 12V HFOCUS 16 CAP Figure 36 12V VAGCCAP 20 Figure 38 12V VOUT 23 26/29 Figure 35 12V BREATH 18 Figure 37 12V VCAP 22 Figure 39 12V EWOUT 24 ...

Page 27

... INTERNAL SCHEMATICS (continued) Figure 40 12V XRAY 25 Figure 42 12V HSIZE 28 Figure 41 12V HOUT 26 Figure 43 12V Pins 30-31 SDA - SCL TDA9110 27/29 ...

Page 28

... C34 820pF R73 R74 5% 1M 10k P1 R75 TP8 10k R77 10k C60 EHT R76 100nF 15k COMP 47k 28/29 J16 J15 1 1 IC2 +5V TDA9110 R39 H/HVIN +5V +5V 4.7k 32 C30 C32 100 F 100nF VSYNCIN SDA 31 MOIRE SCL 30 HLOCKOUT V 29 +12V 100 F 100nF ...

Page 29

... C system, is granted provided that the system conforms to TDA9110 Max. 0.200 0.180 0.023 0.055 0.014 1.120 0.435 0.370 0.500 0.150 29/29 ...

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