TDA9110 STMicroelectronics, TDA9110 Datasheet - Page 18

• Manufacturer Part Number: TDA9110
• Description: Deflection Processor 32-Pin SPDIP
• Manufacturer: STMicroelectronics

Specifications of TDA9110

• Package: 32SPDIP
• Operating Temperature: 0 to 70 °C

TDA9110
OPERATING DESCRIPTION (continued)
Figure 12 : LOCK/UNLOCK Block Diagram
The TDA9110 also includes a Lock/Unlock identifi-
cation block which senses in real time whether the
the PLL1 is locked or not on the incominghorizontal
synchro signal. The resulting information is avail-
able on Hlockout (see Synchro Processor). The
block function is described in Figure 12.
The NOR1 gate receive the phase comparator
output pulses (which also drive the charge pump).
When the PLL1 is locked, we have on point A a very
small negative pulse (about 100ns) at each hori-
zontal cycle, so after the RC filter, there is a high
level on Pin 14 which forces Hlockout to high level.
The hysterisis comparator detects locking when
Pin 14 reachs 6.5V and unlocking when Pin 14
decreases to 6.0V.
When the PLL1 is unlocked, the 100ns negative
pulse on Abecomes much larger and consequently
the average level on Pin 14 decreases. It forces
Hlockout to low level.
The Pin 14 status is approximately the following :
- near 0V when there is no H-Sync
- between 0 and 4V with H-Sync frequency differ-
- between 4 to 8 V when VCO frequency reaches
- near 8V when PLL1 is locked.
It is important to notice that Pin 14 is not an
output pin but is only used for filtering purpose
(see Figure 12).
The lock/unlock information is also available
through the I
II.3 - PLL2
The PLL2 ensures a constant position of the
shaped flyback signal in comparison with the saw-
tooth of the VCO (Figure 13).
The phase comparator of PLL2 (phase type com-
parator) is followed by a charge pump (typical
output current : 0.5mA).
The flyback input consists of an NPN transistor.
This input must be current driven. The maximum
18/29
ent from VCO
H-Sync one (but not already in phase)
From
Phase
Comparator
2
C read.
NOR1
A
20k
220nF
H-Lock CAP
8
recommanded input current is 5mA (see Fig-
ure 14).
The duty cycle is adjustable through I
to 60%. For Start Up safe operation, the initial duty
cycle (afterPower on reset) is 60% in order to avoid
to have a too long conduction of the BU transistor.
Themaximumstoragetime isabout38% (T
Typically, T
Ts max is around 28%.
Figure 13 : PLL2 Timing Diagram
Figure 14 : Flyback Input Electrical Diagram
The duty cycle of H-drive is adjustable between 30% and 60%.
6.5V
Flyback
Internally
Shaped Flyback
H Drive
H Osc
Sawtooth
6V
HFLY
FLY
/T
B
H
Ts
12
is around 20% which means that
Duty Cycle
7/8T
5V
H
20k
GND 0V
3 HLOCKOUT
400
1/8T
H
Q1
2
C from 30%
FLY
6.4V
3.7V
1.6V
/2.T
H
).