CN8237EBGB Mindspeed Technologies, CN8237EBGB Datasheet - Page 365

• Manufacturer Part Number: CN8237EBGB
• Description: ATM SAR 622Mbps 3.3V ABR/CBR/GFR/UBR/VBR 456-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of CN8237EBGB

• Package: 456BGA
• Traffic Class: ABR|CBR|GFR|UBR|VBR
• Utopia Type: Level 1|Level 2
• Host Interface: PCI
• Maximum Data Rate: 622 Mbps
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3.135 V

CN8237
ATM OC-12 ServiceSAR Plus with xBR Traffic Management
28237-DSH-001-C
Table 16-9. Package Interface Pins
16.3 CN8223 PHY Device Connection
Connection to the Mindspeed RS8223 PHY device is shown in
Note that RS8223 requires an active high reset which is opposite from the normal
sense of the PRST* output. Activating HRST_ through the PCI port sets PRST*
low. Once HRST_ returns high, the PHY_RST control must be manipulated by
control register writes to set PHY_RST and PRST* to the desired state. This can
be used to set the PRST* output to the appropriate reset logic sense.
the RS8223. Allowing PAS* to transition while PCLK is transitioning could
cause a glitch in the RS8223 resulting in erroneous operation of the interface.
This timing requirement is met by adding an external delay to the PAS* signal.
Care needs to be taken in the PC layout to insure this condition is met.
PRST*
PCLK
PCS*
PAS*
PDS
PWNR
PWAIT*
PDATA[7:0]
PADDR[12:0]
PINT*
NOTE(S):
(1)
The PAS* signal needs to be stable during PCLK high to avoid a race inside
Direction given with respect to the SAR.
Signal
Mindspeed Technologies
Dir
O
O
O
O
O
O
O
B
O
I
(1)
Normally active low reset to PHY device. Set by a control
register and HRST*.
Processor clock to the PHY device. All interface control
signals are output at the falling edge of this clock. Inputs
are sampled at the rising edge.
Active low chip select output to the PHY device.
Active low address strobe to the PHY
device.
Active low data strobe to the PHY
device.
Read/Write select. A logic 1 on the
output indicates a write cycle, while a
logic 0 indicates a read cycle.
Active low wait input from the PHY device. Allows
extension of the data phase of the interface cycle if the
interface finds this input low. Sampled by PCLK rising and
falling edges.
Bidirectional data bus between the SAR and the PHY
device.
Address bus to the PHY device.
Active low interrupt input from PHY device.
16.0 Electrical and Mechanical Specifications
(Normal Mode)
™
Description
16.3 CN8223 PHY Device Connection
Figure
Active high
address strobe.
Active low read
strobe.
Active low write
strobe.
Description
(Strobed
Mode)
16-16.
16-17