CN8237EBGB Mindspeed Technologies, CN8237EBGB Datasheet - Page 50

• Manufacturer Part Number: CN8237EBGB
• Description: ATM SAR 622Mbps 3.3V ABR/CBR/GFR/UBR/VBR 456-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of CN8237EBGB

• Package: 456BGA
• Traffic Class: ABR|CBR|GFR|UBR|VBR
• Utopia Type: Level 1|Level 2
• Host Interface: PCI
• Maximum Data Rate: 622 Mbps
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3.135 V

2.0 Architecture Overview
2.5 Advanced xBR Traffic Management
Figure 2-9. Multi-Level Model for Prioritizing Segmentation Traffic
2-16
NOTE(S):
Host
(1)
(2)
(3)
(4)
(5)
The user initializes traffic parameters on a per-VCC basis.
User selects priority or round-robin service policy on transmit queues.
The segmentation coprocessor notifies the Traffic Manager when a VCC becomes active, through
reading new entries from the transmit queue.
Each conforming non-CBR VCC is assigned to a priority queue, while conforming CBR VCCs
are simply slated for transmit.
The highest priority conforming cell is formatted and put on the Tx FIFO buffer for transmit.
Buffers
Data
Parameters
Transmit Queues
(1)
Traffic
Control
Tables
VCC
(32)
actually maintained on a per-transmit opportunity basis. In this way, high
priority traffic is transmitted up to its GCRA limits but does not block
lower priority traffic when idle. The CN8237 asynchronously multiplexes
traffic based on the above schemes, as the Tx FIFO buffer empties.
Mindspeed Technologies
Figure 2-9
(2)
Start
Templates
Schedule
Table
ABR
(3)
shows this prioritization as a global set of queues, but it is
Segmentation
ATM OC-12 ServiceSAR Plus with xBR Traffic Management
Coprocessor
xBR Traffic
Manager
Conforming
VCC ID #
16 UBR/VBR/ABR
Priority Queues
Next Tx VCC ID #
SAR
(5)
™
CBR
Full/Empty
(4)
UBR/VBR/ABR
VCC ID #
Tx FIFO
Buffer
28237-DSH-001-C
CN8237
To
PHY
8237_022