ISL23328TFVZ-TK Intersil, ISL23328TFVZ-TK Datasheet
ISL23328TFVZ-TK
Specifications of ISL23328TFVZ-TK
Related parts for ISL23328TFVZ-TK
ISL23328TFVZ-TK Summary of contents
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... FIGURE 2. V CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 Intersil (and design) and XDCP are trademarks owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners 2 C bus/logic power supply ...
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Block Diagram V LOGIC SCL SDA LEVEL I/O A0 SHIFTER BLOCK A1 A2 Pin Configurations ISL23328 (14 LD TSSOP) TOP VIEW GND LOGIC SDA 3 SCL ISL23328 (16 LD UTQFN) ...
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... Ordering Information PART NUMBER (Note 4) PART MARKING ISL23328TFVZ (Note 2) 23328 TFVZ ISL23328TFVZ-T7A (Notes 1, 2) 23328 TFVZ ISL23328TFVZ-TK (Notes 1, 2) 23328 TFVZ ISL23328UFVZ (Note 2) 23328 UFVZ ISL23328UFVZ-T7A (Notes 1, 2) 23328 UFVZ ISL23328UFVZ-TK (Notes 1, 2) 23328 UFVZ ISL23328WFVZ (Note 2) 23328 WFVZ ISL23328WFVZ-T7A (Notes 1, 2) ...
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... Thermal Resistance (Typical TSSOP Package (Notes UTQFN Package (Notes Maximum Junction Temperature (Plastic Package .+150°C Storage Temperature Range .-65°C to +150°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C V Supply Voltage 1. Supply Voltage ...
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Analog Specifications V = 2.7V to 5.5V Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued) SYMBOL PARAMETER VOLTAGE DIVIDER MODE ( RH; measured at RW, unloaded) CC INL Integral Non-linearity, ...
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Analog Specifications V = 2.7V to 5.5V Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued) SYMBOL PARAMETER R Offset, Wiper at 0 Position offset (Note 15) Rmatch DCP to DCP Matching (Note 22) TCR ...
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Operating Specifications Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued) SYMBOL PARAMETER t Wiper Response Time DCP tShdnRec DCP Recall Time from Shutdown Mode Ramp Rate CC, LOGIC CC , LOGIC Ramp ...
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Serial Interface Specification SYMBOL PARAMETER t START Condition Hold Time HD:STA t Input Data Set-up Time SU:DAT t Input Data Hold Time HD:DAT t STOP Condition Set-up Time SU:STO t STOP Condition Hold Time for Read HD:STO or Write t ...
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DCP Macro Model Timing Diagrams SDA vs SCL Timing SCL t SU:STA t HD:STA SDA (INPUT TIMING) SDA (OUTPUT TIMING) A0, A1, and A2 Pin Timing START SCL SDA A0, A1 ISL23328 R TOTAL ...
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Typical Performance Curves 0.20 0.10 0.00 -0.10 -0. TAP POSITION (DECIMAL) FIGURE 3. 10kΩ DNL vs TAP POSITION, V 0.30 0.15 0.00 -0.15 -0. TAP POSITION (DECIMAL) FIGURE 5. 10kΩ INL vs TAP POSITION, ...
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Typical Performance Curves 0.30 0.15 0.00 -0.15 -0. TAP POSITION (DECIMAL) FIGURE 9. 10kΩ RINL vs TAP POSITION, V 100 +25° -40° TAP POSITION (DECIMAL) FIGURE 11. 10kΩ WIPER ...
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Typical Performance Curves 500 400 300 200 100 TAP POSITION (DECIMAL) FIGURE 15. 10kΩ TCr vs TAP POSITION TAP POSITION (DECIMAL) FIGURE 17. 100kΩ TCv vs TAP POSITION, ...
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Typical Performance Curves 1V/DIV 0.2µs/DIV FIGURE 21. WIPER LARGE SIGNAL SETTLING TIME CH1: RH TERMINAL CH2: RW TERMINAL 0.5V/DIV, 0.2µs/DIV -3dB FREQUENCY = 1.4MHz AT MIDDLE TAP FIGURE 23. 10kΩ -3dB CUT OFF FREQUENCY Functional Pin Descriptions Potentiometers Pins RH ...
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SERIAL CLOCK (SCL) 2 This input is the serial clock of the I C serial interface. SCL requires an external pull-up resistor, since a master is an open drain output. DEVICE ADDRESS (A2, A1, A0) The address inputs are used ...
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POWER-UP MID SCALE = 40H USER PROGRAMMED SHDN ACTIVATED SHDN RELEASED SHDN MODE 0 TIME (s) FIGURE 26. SHUTDOWN MODE WIPER RESPONSE Serial Interface 2 The ISL23328 supports bidirectional bus oriented protocol. The protocol ...
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SCL FROM MASTER SDA OUTPUT FROM TRANSMITTER SDA OUTPUT FROM RECEIVER START SIGNALS FROM THE MASTER SIGNAL AT SDA SIGNALS FROM THE SLAVE S T SIGNALS A IDENTIFICATION FROM THE R BYTE WITH MASTER T R SIGNAL AT ...
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Applications Information V Requirements LOGIC V should be powered continuously during normal operation. LOGIC In a case where turning V OFF is necessary LOGIC recommended to ground the V pin of the ISL23328. LOGIC Grounding the V pin ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. ...
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Package Outline Drawing M14.173 14 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP) Rev 3, 10/09 1 5.00 ±0.10 14 6.40 4.40 ±0. 0. 0.65 TOP VIEW H C SEATING PLANE 0.10 C SIDE VIEW ...
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... Maximum package warpage is 0.05mm. 8. Maximum allowable burrs is 0.076mm in all directions. TERMINAL TIP 9. JEDEC Reference MO-255. 10. For additional information, to assist with the PCB Land Pattern Design effort, see Intersil Technical Brief TB389. 1.40 0.40 0.20 MILLIMETERS MIN NOMINAL ...