ISL23328TFVZ-TK Intersil, ISL23328TFVZ-TK Datasheet - Page 7

• Manufacturer Part Number: ISL23328TFVZ-TK
• Description: IC DGTL POT 2CH 100K 14TSSOP
• Manufacturer: Intersil
• Series: XDCP™r

Specifications of ISL23328TFVZ-TK

• Taps: 128
• Resistance (ohms): 100K
• Number Of Circuits: 2
• Temperature Coefficient: 45 ppm/°C Typical
• Memory Type: Volatile
• Interface: I²C (Device Address)
• Voltage - Supply: 1.2 V ~ 5.5 V, 1.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Operating Specifications
Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued)
Serial Interface Specification
V
tShdnRec
(Note 20)
CC,
SYMBOL
Hysteresis
Ramp
SYMBOL
t
t
DCP
V
t
SU:STA
t
t
C
f
LOGIC
V
HIGH
t
LOW
V
V
t
BUF
SCL
AA
OL
pin
sp
IH
IL
Wiper Response Time
DCP Recall Time from Shutdown Mode
V
CC ,
Input LOW Voltage
Input HIGH Voltage
SDA and SCL Input Buffer
Hysteresis
SDA Output Buffer LOW Voltage
SDA, SCL Pin Capacitance
SCL Frequency
Pulse Width Suppression Time at
SDA and SCL Inputs
SCL Falling Edge to SDA Output
Data Valid
Time the Bus Must be Free Before
the Start of a New Transmission
Clock LOW Time
Clock HIGH Time
START Condition Set-up Time
V
LOGIC
Ramp Rate
PARAMETER
PARAMETER
7
V
CC
= 2.7V to 5.5V, V
For SCL, SDA, A0, A1, A2 unless otherwise noted.
V
V
I
I
Any pulse narrower than the
max spec is suppressed
SCL falling edge crossing 30%
of V
30% to 70% of V
SDA crossing 70% of V
during a STOP condition, to
SDA crossing 70% of V
during the following START
condition
Measured at the 30% of
V
Measured at the 70% of
V
SCL rising edge to SDA falling
edge; both crossing 70% of
V
OL
OL
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
W option; SCL rising edge of the
acknowledge bit after data byte to wiper
new position from 10% to 90% of the
final value.
U option; SCL rising edge of the
acknowledge bit after data byte to wiper
new position from 10% to 90% of the
final value.
T option; SCL rising edge of the
acknowledge bit after data byte to wiper
new position from 10% to 90% of the
final value.
SCL rising edge of the acknowledge bit
after ACR data byte to wiper recalled
position and RH connection
Ramp monotonic at any level
= 3mA, V
= 1.5mA, V
LOGIC
TEST CONDITIONS
> 2V
< 2V
crossing
crossing
, until SDA exits the
LOGIC
ISL23328
TEST CONDITIONS
LOGIC
LOGIC
= 1.2V to 5.5V over recommended operating conditions unless otherwise stated.
LOGIC
> 2V
< 2V
LOGIC
LOGIC
window
0.05 x V
0.7 x V
0.1 x V
(Note 19)
1300
1300
MIN
600
600
-0.3
0
LOGIC
LOGIC
LOGIC
(Note 19)
0.01
MIN
(Note 7)
TYP
10
(Note 7)
TYP
0.4
1.5
3.5
1.5
V
0.3 x V
0.2 x V
LOGIC
(Note 19)
MAX
400
900
0.4
50
(Note 19)
LOGIC
LOGIC
+ 0.3
MAX
50
August 19, 2011
UNITS
kHz
pF
ns
ns
ns
ns
ns
ns
UNITS
V/ms
V
V
FN7902.0
V
V
V
V
µs
µs
µs
µs