P87LPC760BDH NXP Semiconductors, P87LPC760BDH Datasheet - Page 14

• Manufacturer Part Number: P87LPC760BDH
• Description: MCU 8-Bit 87LP 80C51 CISC 1KB EPROM 5V 14-Pin TSSOP Tube
• Manufacturer: NXP Semiconductors

Specifications of P87LPC760BDH

• Package: 14TSSOP
• Device Core: 80C51
• Family Name: 87LP
• Maximum Speed: 20 MHz
• Ram Size: 128 Byte
• Program Memory Size: 1 KB
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Program Memory Type: EPROM
• Number Of Programmable I/os: 12
• Interface Type: I2C/UART
• Operating Temperature: 0 to 70 °C
• Number Of Timers: 2

Philips Semiconductors
I
The I
between devices connected to the bus. The main bus features are:
The I
required to drive the I
which in addition to including the necessary arbitration and framing
error checks, includes clock stretching and a bus timeout timer. The
interface is synchronized to software either through polled loops or
interrupts.
Refer to the application note AN422, entitled “Using the 8XC751
Microcontroller as an I
the 8xC76x I
The P87LPC760 I
and 87C752 except for the following details:
Timer I is used to both control the timing of the I
detect a “bus locked” condition, by causing an interrupt when
nothing happens on the I
time while a transmission is in progress. If this interrupt occurs, the
program has the opportunity to attempt to correct the fault and
resume I
Six time spans are important in I
2002 Mar 07
2
C Serial Interface
Bidirectional data transfer between masters and slaves.
Serial addressing of slaves (no added wiring).
Acknowledgment after each transferred byte.
Multimaster bus.
Arbitration between simultaneously transmitting masters without
corruption of serial data on bus.
The interrupt vector addresses for both the I
Timer I interrupt.
The I
The location of the I
SFR it is located within (EI2 is Bit 0 in IEN1).
The location of the Timer I interrupt enable bit and the name of the
SFR it is located within (ETI is Bit 7 in IEN1).
The I
The MINIMUM HIGH time for SCL when this device is the master.
The MINIMUM LOW time for SCL when this device is a master.
This is not very important for a single-bit hardware interface like
this one, because the SCL low time is stretched until the software
responds to the I
meets or exceeds the MIN LO time. In cases where the software
responds within MIN HI + MIN LO time, timer I will ensure that the
minimum time is met.
The MINIMUM SCL HIGH TO SDA HIGH time in a stop condition.
The MINIMUM SDA HIGH TO SDA LOW time between I
and start conditions (4.7ms, see I
The MINIMUM SDA LOW TO SCL LOW time in a start condition.
The MAXIMUM SCL CHANGE time while an I
progress. A frame is in progress between a start condition and the
following stop condition. This time span serves to detect a lack of
software response on this device as well as external I
problems. SCL “stuck low” indicates a faulty master or slave. SCL
Low power, low price, low pin count (14 pin)
microcontroller with 1 kbyte OTP
2
2
C bus uses two wires (SDA and SCL) to transfer information
C subsystem includes hardware to simplify the software
2
2
C SFR addresses (I2CON, I2CFG, I2DAT).
C and Timer I interrupts have a settable priority.
2
C operation.
2
C interface and sample driver routines.
2
C implementation duplicates that of the 87C751
2
C flags. The software response time normally
2
2
C bus. The hardware is a single bit interface
2
C interrupt enable bit and the name of the
C Bus Master” for additional discussion of
2
C bus for an inordinately long period of
2
C operation and are insured by timer I:
2
C specification).
2
C interrupt and the
2
2
C bus and also to
C frame is in
2
C
2
C stop
11
The first five of these times are 4.7 ms (see I
are covered by the low order three bits of timer I. Timer I is clocked
by the P87LPC760 CPU clock. Timer I can be pre-loaded with one
of four values to optimize timing for different oscillator frequencies.
At lower frequencies, software response time is increased and will
degrade maximum performance of the I
register I2CFG description for prescale values (CT0, CT1).
The MAXIMUM SCL CHANGE time is important, but its exact span
is not critical. The complete 10 bits of timer I are used to count out
the maximum time. When I
cleared by transitions on the SCL pin. The timer does not run
between I
recently than the last start). When this counter is running, it will carry
out after 1020 to 1023 machine cycles have elapsed since a change
on SCL. A carry out causes a hardware reset of the I
and generates an interrupt if the Timer I interrupt is enabled. In
cases where the bus hang-up is due to a lack of software response
by this device, the reset releases SCL and allows I
among other devices to continue.
Timer I is enabled to run, and will reset the I
overflow, if the TIRUN bit in the I2CFG register is set. The Timer I
interrupt may be enabled via the ETI bit in IEN1, and its priority set
by the PTIH and PTI bits in the IP1H and IP1 registers respectively.
I
If I
interrupt will occur whenever the ATN flag is set by a start, stop,
arbitration loss, or data ready condition (refer to the description of
ATN following). In practice, it is not efficient to operate the I
interface in this fashion because the I
would somehow have to distinguish between hundreds of possible
conditions. Also, since I
software may execute faster if the code simply waits for the I
interface.
Typically, the I
condition at an idle slave device, or a stop condition at an idle
master device (if it is waiting to use the I
accomplished by enabling the I
aforementioned conditions.
Reading I2CON
RDAT
ATN
DRDY
2
C Interrupts
“stuck high” may mean a faulty device, or that noise induced onto
the I
2
C interrupts are enabled (EA and EI2 are both set to 1), an I
2
C bus caused all masters to withdraw from I
2
C frames (i.e., whenever reset or stop occurred more
The data from SDA is captured into “Receive DATa”
whenever a rising edge occurs on SCL. RDAT is also
available (with seven low-order zeros) in the I2DAT
register. The difference between reading it here and
there is that reading I2DAT clears DRDY, allowing the
I
seven bits of a received byte are read from
I2DAT, while the 8th is read here. Then I2DAT can be
written to send the Acknowledge bit and clear DRDY.
“ATteNtion” is 1 when one or more of DRDY, ARL, STR,
or STP is 1. Thus, ATN comprises a single bit that can
be tested to release the I
loop.”
“Data ReaDY” (and thus ATN) is set when a rising edge
occurs on SCL, except at idle slave. DRDY is cleared
by writing CDR = 1, or by writing or reading the I2DAT
register. The following low period on SCL is stretched
until the program responds by clearing DRDY.
2
2
C to proceed on to another bit. Typically, the first
C interrupt should only be used to indicate a start
2
C can operate at a fairly high rate, the
2
C operation is enabled, this counter is
2
C interrupt only during the
2
2
C interrupt service routine
C service routine from a “wait
2
2
C bus. See special function
C bus). This is
2
P87LPC760
2
C interface upon
C specification) and
2
2
C operation
Preliminary data
C arbitration.
2
C interface
2
C
2
C
2
C