P87LPC760BDH NXP Semiconductors, P87LPC760BDH Datasheet - Page 22

• Manufacturer Part Number: P87LPC760BDH
• Description: MCU 8-Bit 87LP 80C51 CISC 1KB EPROM 5V 14-Pin TSSOP Tube
• Manufacturer: NXP Semiconductors

Specifications of P87LPC760BDH

• Package: 14TSSOP
• Device Core: 80C51
• Family Name: 87LP
• Maximum Speed: 20 MHz
• Ram Size: 128 Byte
• Program Memory Size: 1 KB
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Program Memory Type: EPROM
• Number Of Programmable I/os: 12
• Interface Type: I2C/UART
• Operating Temperature: 0 to 70 °C
• Number Of Timers: 2

1. See Table 4, Port Output Configuration Settings.
Philips Semiconductors
Keyboard Interrupt (KBI)
The Keyboard Interrupt function is intended primarily to allow a
single interrupt to be generated when any key is pressed on a
keyboard or keypad connected to specific pins of the P87LPC760,
as shown in Figure 14. This interrupt may be used to wake up the
CPU from Idle or Power Down modes. This feature is particularly
useful in handheld, battery powered systems that need to carefully
manage power consumption yet also need to be convenient to use.
The P87LPC760 allows any pin of port 0 to be enabled to cause this
interrupt. Port pins are enabled by the setting of bits in the KBI
register, as shown in Figure 15. The Keyboard Interrupt Flag (KBF)
in the AUXR1 register is set when any enabled pin is pulled low
while the KBI interrupt function is active. An interrupt will generated
if it has been enabled. Note that the KBF bit must be cleared by
software.
2002 Mar 07
P2M1
Low power, low price, low pin count (14 pin)
microcontroller with 1 kbyte OTP
BIT
P2M1.7
P2M1.6
P2M1.5
P2M1.4
P2M1.2
P2M1.1, P2M1.0
Address: A4h
Not Bit Addressable
SYMBOL
ENCLK
T0OE
P2S
P1S
P0S
—
P2S
7
FUNCTION
When P2S = 1, this bit enables Schmitt trigger inputs on Port 2.
When P1S = 1, this bit enables Schmitt trigger inputs on Port 1.
When P0S = 1, this bit enables Schmitt trigger inputs on Port 0.
When ENCLK is set and the 87LPC760 is configured to use the on-chip RC oscillator, a clock
output is enabled on the X2 pin (P2.0). Refer to the Oscillator section for details.
When set, the P1.2 pin is toggled whenever Timer 0 overflows. The output frequency is therefore
one half of the Timer 0 overflow rate. Refer to the Timer/Counters section for details.
These bits, along with the matching bits in the P2M2 register, control the output configuration of
P2.1 and P2.0 respectively
P1S
6
Figure 13. Port 2 Mode Register 1 (P2M1)
P0S
5
ENCLK
1
4
.
19
Due to human time scales and the mechanical delay associated with
keyswitch closures, the KBI feature will typically allow the interrupt
service routine to poll port 0 in order to determine which key was
pressed, even if the processor has to wake up from Power Down
mode. Refer to the section on Power Reduction Modes for details.
3
–
T0OE
2
(P2M1.1)
1
(P2M1.0)
0
Reset Value: 00h
P87LPC760
SU01535
Preliminary data