P87LPC760BDH NXP Semiconductors, P87LPC760BDH Datasheet - Page 15

• Manufacturer Part Number: P87LPC760BDH
• Description: MCU 8-Bit 87LP 80C51 CISC 1KB EPROM 5V 14-Pin TSSOP Tube
• Manufacturer: NXP Semiconductors

Specifications of P87LPC760BDH

• Package: 14TSSOP
• Device Core: 80C51
• Family Name: 87LP
• Maximum Speed: 20 MHz
• Ram Size: 128 Byte
• Program Memory Size: 1 KB
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Program Memory Type: EPROM
• Number Of Programmable I/os: 12
• Interface Type: I2C/UART
• Operating Temperature: 0 to 70 °C
• Number Of Timers: 2

1. Due to the manner in which bit addressing is implemented in the 80C51 family, the I2CON register should never be altered by use of the
Philips Semiconductors
2002 Mar 07
Low power, low price, low pin count (14 pin)
microcontroller with 1 kbyte OTP
I2CON
I2DAT
SETB, CLR, CPL, MOV (bit), or JBC instructions. This is due to the fact that read and write functions of this register are different. Testing of
I2CON bits via the JB and JNB instructions is supported.
BIT
I2CON.7
I2CON.6
I2CON.5
I2CON.4
I2CON.3
I2CON.2
I2CON.1
I2CON.0
BIT
I2DAT.7
I2DAT.6–0
“
“
“
“
“
“
“
“
“
Address: D8h
Bit Addressable
Address: D9h
Not Bit Addressable
SYMBOL
SYMBOL
MASTER
WRITE
WRITE
READ
READ
DRDY
CSTR
RDAT
CARL
CSTP
XSTR
XSTP
RDAT
XDAT
IDLE
CDR
CXA
ATN
ARL
STR
STP
—
–
1
RDAT
RDAT
XDAT
CXA
7
7
FUNCTION
Read: the most recently received data bit.
Write: clears the transmit active flag.
Read: ATN = 1 if any of the flags DRDY, ARL, STR, or STP = 1.
Write: in the I
is needed again.
Read: Data Ready flag, set when there is a rising edge on SCL.
Write: writing a 1 to this bit clears the DRDY flag.
Read: Arbitration Loss flag, set when arbitration is lost while in the transmit mode.
Write: writing a 1 to this bit clears the CARL flag.
Read: Start flag, set when a start condition is detected at a master or non-idle slave.
Write: writing a 1 to this bit clears the STR flag.
Read: Stop flag, set when a stop condition is detected at a master or non-idle slave.
Write: writing a 1 to this bit clears the STP flag.
Read: indicates whether this device is currently as bus master.
Write: writing a 1 to this bit causes a repeated start condition to be generated.
Read: undefined.
Write: writing a 1 to this bit causes a stop condition to be generated.
FUNCTION
Read: the most recently received data bit, captured from SDA at every rising edge of SCL. Reading
I2DAT also clears DRDY and the Transmit Active state.
Write: sets the data for the next transmitted bit. Writing I2DAT also clears DRDY and sets the
Transmit Active state.
Unused.
IDLE
ATN
—
—
6
6
2
C slave mode, writing a 1 to this bit causes the I
Figure 6. I
DRDY
Figure 7. I
CDR
—
—
5
5
2
CARL
C Control Register (I2CON)
ARL
2
—
—
C Data Register (I2DAT)
4
4
12
CSTR
STR
—
—
3
3
CSTP
STP
—
—
2
2
MASTER
XSTR
—
—
1
1
2
C hardware to ignore the bus until it
XSTP
—
—
—
0
0
Reset Value: 81h
Reset Value: xxh
P87LPC760
Preliminary data
SU01155
SU01156