P89V51RD2FN NXP Semiconductors, P89V51RD2FN Datasheet - Page 55

• Manufacturer Part Number: P89V51RD2FN
• Description: MCU 8-Bit 89V 80C51 CISC 64KB Flash 5V 40-Pin PDIP Tube
• Manufacturer: NXP Semiconductors

Specifications of P89V51RD2FN

• Package: 40PDIP
• Device Core: 80C51
• Family Name: 89V
• Maximum Speed: 40 MHz
• Ram Size: 1 KB
• Program Memory Size: 64 KB
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 32
• Interface Type: SPI/UART
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 3

NXP Semiconductors
Table 43.
P89V51RB2_RC2_RD2_5
Product data sheet
Description
Ext. Int0
Brownout
T0
Ext. Int1
T1
PCA
UART/SPI
T2
Interrupt polling sequence
6.10 Security bit
6.11 Interrupt priority and polling sequence
Interrupt flag
IE0
-
TF0
IE1
TF1
CF/CCFn
TI/RI/SPIF
TF2, EXF2
The Security Bit protects against software piracy and prevents the contents of the flash
from being read by unauthorized parties in Parallel Programmer mode. It also protects
against code corruption resulting from accidental erasing and programming to the internal
flash memory.
When the Security Bit is activated all parallel programming commands except for
Chip-Erase are ignored (thus the device cannot be read). However, ISP reading, writing,
or erasing of the user’s code can still be performed if the serial number and length has not
been programmed. Therefore, when a user requests to program the Security Bit, the
programmer should prompt the user and program a serial number into the device.
The device supports eight interrupt sources under a four level priority scheme.
summarizes the polling sequence of the supported interrupts. Note that the SPI serial
interface and the UART share the same interrupt vector. (See
Vector address Interrupt
0003H
004BH
000BH
0013H
001BH
0033H
0023H
002BH
Rev. 05 — 12 November 2009
enable
EX0
EBO
ET0
EX1
ET1
EC
ES
ET2
Interrupt
priority
PX0/H
PBO/H
PT0/H
PX1/H
PT1/H
PPCH
PS/H
PT2/H
P89V51RB2/RC2/RD2
8-bit microcontrollers with 80C51 core
Service
priority
1 (highest)
2
3
4
5
6
7
8
Figure
27).
© NXP B.V. 2009. All rights reserved.
Wake-up
power-down
yes
no
no
yes
no
no
no
no
Table 43
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