RC28F128P33BF60A Micron Technology Inc, RC28F128P33BF60A Datasheet - Page 18

• Manufacturer Part Number: RC28F128P33BF60A
• Manufacturer: Micron Technology Inc

Specifications of RC28F128P33BF60A

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Table 5:
6.2
Table 6:
Datasheet
18
Configuration
blank check
Program
Suspend
Mode
other
Erase
Mode
Read
Command Codes and Definitions (Sheet 3 of 3)
Command Bus Cycles (Sheet 1 of 2)
Device Command Bus Cycles
Device operations are initiated by writing specific device commands to the CUI. See
Table 6, “Command Bus Cycles” on page
array data including Word Program and Block Erase commands. Writing either
command to the CUI initiates a sequence of internally-timed functions that culminate in
the completion of the requested task. However, the operation can be aborted by either
asserting RST# or by issuing an appropriate suspend command.
Read Array
Read Device
Identifier
Read CFI
Read Status Register
Clear Status Register
Word Program
Buffered Program
Buffered Enhanced
Factory Program
(BEFP)
Block Erase
Program/Erase
Suspend
Program/Erase
Resume
Code
0xBC
0xD0
0x60
0x03
0xEB
Command
(4)
Read Configuration
Register Setup
Read Configuration
Register
Blank Check
Blank Check
Confirm
Extended Function
Interface
Device Mode
(3)
Cycles
Bus
≥ 2
≥ 2
> 2
> 2
1
2
1
2
2
1
1
First cycle of a 2-cycle command; prepares the CUI for device read
configuration. If the Set Read Configuration Register command (0x03) is not
the next command, the CUI sets Status Register bits SR.5 and SR.4,
indicating a command sequence error.
If the previous command was Read Configuration Register Setup (0x60), the
CUI latches the address and writes A[16:1]to the Read Configuration
Register. Following a Configure RCR command, subsequent read operations
access array data.
First cycle of a 2-cycle command; initiates the Blank Check operation on a
main block.
Second cycle of blank check command sequence; it latches the block address
and executes blank check on the main array block.
This command is used in extended function interface. first cycle of a multiple-
cycle command second cycle is a Sub-Op-Code, the data written on third
cycle is one less than the word count; the allowable value on this cycle are 0
through 511. The subsequent cycles load data words into the program buffer
at a specified address until word count is achieved.
Oper
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
First Bus Cycle
Addr
DnA
DnA
DnA
DnA
DnA
DnA
DnA
WA
WA
WA
BA
18. Several commands are used to modify
(1)
Data
0xD0
0x90
0x98
0x70
0x50
0x40
0xE8
0x80
0x20
0xB0
0xFF
Description
(2)
Oper
Write
Write
Write
Write
Read
Read
Read
-
-
-
-
Second Bus Cycle
DBA + CFI-A
Order Number: 208034-04
DBA + IA
Addr
DnA
WA
WA
WA
BA
-
-
-
-
(1)
P33-65nm
Data
CFI-D
0xD0
0xD0
N - 1
SRD
WD
Jul 2011
ID
-
-
-
-
(2)