RC28F128P33BF60A Micron Technology Inc, RC28F128P33BF60A Datasheet - Page 24

• Manufacturer Part Number: RC28F128P33BF60A
• Manufacturer: Micron Technology Inc

Specifications of RC28F128P33BF60A

• Lead Free Status / Rohs Status: Supplier Unconfirmed

8.3.1
Table 9:
Note:
Table 10: BEFP Considerations
Notes:
1.
2.
3.
8.3.2
Note:
Datasheet
24
Case Temperature
VCC
VPP
Setup and Confirm
Programming
Buffer Alignment
Cycling
Programming blocks
Suspend
Programming the flash
memory array
Parameter/Issue
Parameter/Issue
Word buffer boundaries in the array are determined by A[8:1] (0x00 through 0xFF); the alignment start point is A[8:1] =
0x00.
Some degradation in performance may occur is this limit is exceeded, but the internal algorithm continues to work
properly.
If the internal address counter increments beyond the block’s maximum address, addressing wraps around to the
beginning of the block.
If the number of words is less than 256, remaining locations must be filled with 0xFFFF.
BEFP Requirements
With adequate continuity testing, programming equipment can rely on the WSM’s
internal verification to ensure that the device has programmed properly. This eliminates
the external post-program verification and its associated overhead.
BEFP Requirements and Considerations
BEFP Setup Phase
After receiving the BEFP Setup and Confirm command sequence, Status Register bit
SR.7 (Ready) is cleared, indicating that the WSM is busy with BEFP algorithm startup. A
delay before checking SR.7 is required to allow the WSM enough time to perform all of
its setups and checks (Block-Lock status, VPP level, etc.). If an error is detected, SR.4
is set and BEFP operation terminates. If the block was found to be locked, SR.1 is also
set. SR.3 is set if the error occurred due to an incorrect VPP level.
Reading from the device after the BEFP Setup and Confirm command sequence outputs
Status Register data. Do not issue the Read Status Register command; it will be
interpreted as data to be loaded into the buffer.
T
Nominal Vcc
Driven to V
Target block must be unlocked before issuing the BEFP Setup and Confirm commands.
The first-word address (WA0) of the block to be programmed must be held constant
from the setup phase through all data streaming into the target block, until transition
to the exit phase is desired.
WA0 must align with the start of an array buffer boundary.
For optimum performance, cycling must be limited below 50 erase cycles per block.
BEFP programs one block at a time; all buffer data must fall within a single block.
BEFP cannot be suspended.
Programming to the flash memory array can occur only when the buffer is full.
C
= 30
°
C ± 10°C
PPH
Requirement
Requirement
Order Number: 208034-04
-
-
-
-
-
1
1
2
-
3
P33-65nm
Notes
Notes
Jul 2011