RC28F128P33BF60A Micron Technology Inc, RC28F128P33BF60A Datasheet - Page 38

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RC28F128P33BF60A

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RC28F128P33BF60A
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Manufacturer
Micron Technology Inc
Datasheet

Specifications of RC28F128P33BF60A

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Table 15: WAIT Functionality Table
11.1.6
Figure 11: Data Hold Timing
Datasheet
38
CE# = ‘1’, OE# = ‘X’ or CE# = ‘0’, OE# = ‘1’
CE# =’0’, OE# = ‘0’
Synchronous Array Reads
Synchronous Non-Array Reads
All Asynchronous Reads
All Writes
Notes:
1.
2.
Data Hold
Data Hold
Active: WAIT is asserted until data becomes valid, then deasserts.
When OE# = V
1 CLK
2 CLK
Data Output Configuration (RCR.9)
The Data Output Configuration (DOC) bit, RCR.9 determines whether a data word
remains valid on the data bus for one or two clock cycles. This period of time is called
the “data cycle”. When DOC is set, output data is held for two clocks (default). When
DOC is cleared, output data is held for one clock (see
page
delay should be considered when determining whether to hold output data for one or
two clocks. A method for determining the Data Hold configuration is shown below:
To set the device at one clock data hold for subsequent reads, the following condition
must be satisfied:
For example, with a clock frequency of 40 MHz, the clock period is 25 ns. Assuming
t
The equation is satisfied and data will be available at every clock period with data hold
setting at one clock. If t
2 clock periods must be used.
CHQV
IH
38). The processor’s data setup time and the flash memory’s clock-to-data output
= 20 ns and t
during writes, WAIT = High-Z.
D[15:0] [Q]
D[15:0] [Q]
t
t
DATA
20 ns + 4 ns
CHQV
Condition
CLK [C]
= Data set up to Clock (defined by CPU)
(ns)
DATA
+
t
DATA
25 ns
CHQV (ns) +
= 4 ns. Applying these values to the formula above:
(ns)
Output
Valid
t
DATA
One CLK Period (ns)
Output
Valid
(ns) > One CLK Period (ns), data hold setting of
High-Z
Active
Active
Active
Deasserted
High-Z
Output
Valid
Figure 11, “Data Hold Timing” on
Output
WAIT
Valid
Output
Valid
Order Number: 208034-04
P33-65nm
Notes
1,2
Jul 2011
1
1
1
1
1

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