DS21552L+ Maxim Integrated Products, DS21552L+ Datasheet - Page 67

• Manufacturer Part Number: DS21552L+
• Description: IC TXRX T1 1-CHIP 5V 100-LQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS21552L+

• Function: Single-Chip Transceiver
• Interface: E1, HDLC, J1, T1
• Number Of Circuits: 1
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 75mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Includes: DSX-1 and CSU Line Build-Out Generator, HDLC Controller, In-Band Loop Code Generator and Detector
• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 64 Kbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 75 mA (Typ)
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Ic Interface Type: Parallel, Serial
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: LQFP
• No. Of Pins: 100
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

DS21352/DS21552
Firmware,
which
can
be
retrieved
from
the
Web
site
(www.dalsemi.com/Prod_info
/Telecom/t1_e1_tools.html), was developed to implement the FDL.
The code for the DS2151
incorporates the LAPD protocol and can be used with any of the 51/52/352/552 SCTs. The code for the
DS2152 can be used with the 52/352/552 SCTs.
15.3 HDLC AND BOC CONTROLLER FOR THE FDL
15.3.1 GENERAL OVERVIEW
The device contains a complete HDLC controller with 64–byte buffers in both the transmit and receive
directions as well as separate dedicated hardware for Bit Oriented Codes (BOC). The HDLC controller
performs all the necessary overhead for generating and receiving Performance Report Messages (PRM)
as described in ANSI T1.403 and the messages as described in AT&T TR54016. The HDLC controller
automatically generates and detects flags, generates and checks the CRC check sum, generates and
detects abort sequences, stuffs and destuffs zeros (for transparency), and byte aligns to the FDL data
stream. The 64–byte buffers in the HDLC controller are large enough to allow a full PRM to be received
or transmitted without host intervention. The BOC controller will automatically detect incoming BOC
sequences and alert the host. When the BOC ceases, the device will also alert the host. The user can set
the device up to send any of the possible 6–bit BOC codes.
There are thirteen registers that the host will use to operate and control the operation of the HDLC and
BOC controllers. A brief description of the registers is shown in Table 15-2.
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