DS21552L+ Maxim Integrated Products, DS21552L+ Datasheet - Page 73

• Manufacturer Part Number: DS21552L+
• Description: IC TXRX T1 1-CHIP 5V 100-LQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS21552L+

• Function: Single-Chip Transceiver
• Interface: E1, HDLC, J1, T1
• Number Of Circuits: 1
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 75mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Includes: DSX-1 and CSU Line Build-Out Generator, HDLC Controller, In-Band Loop Code Generator and Detector
• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 64 Kbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 75 mA (Typ)
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Ic Interface Type: Parallel, Serial
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: LQFP
• No. Of Pins: 100
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

RHIR: RECEIVE HDLC INFORMATION REGISTER (Address=03 Hex)
NOTE:
The RABT, RCRCE, ROVR, and RVM bits are latched and will be cleared when read.
SYMBOL
REMPTY
(MSB)
RABT
CBYTE
OBYTE
RCRCE
ROVR
RABT
RVM
POK
RCRCE
POSITION
RHIR.7
RHIR.6
RHIR.5
RHIR.4
RHIR.3
RHIR.2
RHIR.1
RHIR.0
ROVR
NAME AND DESCRIPTION
Abort Sequence Detected. Set whenever the HDLC controller sees 7 or more ones in a
row.
CRC Error. Set when the CRC checksum is in error.
Overrun. Set when the HDLC controller has attempted to write a byte into an already full
receive FIFO.
Valid Message. Set when the HDLC controller has detected and checked a complete
HDLC packet.
Empty. A real–time bit that is set high when the receive FIFO is empty.
Packet OK. Set when the byte available for reading in the receive FIFO is the last byte of
a valid message (and hence no abort was seen, no overrun occurred, and the CRC was
correct).
Closing Byte. Set when the byte available for reading in the receive FIFO is the last byte
of a message (whether the message was valid or not).
Opening Byte. Set when the byte available for reading in the receive FIFO is the first byte
of a message.
RVM
73 of 137
REMPTY
POK
CBYTE
OBYTE
(LSB)