SC16C850SVIBS,151 NXP Semiconductors, SC16C850SVIBS,151 Datasheet - Page 32

• Manufacturer Part Number: SC16C850SVIBS,151
• Description: IC UART SINGLE W/FIFO 32-HVQFN
• Manufacturer: NXP Semiconductors

Specifications of SC16C850SVIBS,151

• Features: Programmable
• Number Of Channels: 1, UART
• Fifo's: 128 Byte
• Protocol: RS485
• Voltage - Supply: 1.8V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 32-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-4707; 935286785151; SC16C850SVIBS-S

NXP Semiconductors
SC16C850SV
Product data sheet
7.20 Sampling rate (SAMPR)
7.21 RS-485 turn-around time delay (RS485TIME)
7.22 Advanced Feature Control Register 1 (AFCR1)
Bit 1 and bit 0 of this register program the device’s sampling rate.
Table 30.
The value in this register controls the turn-around time of the external line transceiver in
bit time. In automatic 9-bit mode, the RTS or DTR pin is used to control the direction of the
line driver, after the last bit of data has been shifted out of the transmit shift register the
UART will count down the value in this register. When the count value reaches zero, the
UART will assert the RTS or DTR pin (logic 0) to turn the external RS-485 transceiver
around for receiving.
Table 31.
Table 32.
Bit
7:2
1:0
Bit
7:0
Bit
7:5
4
3
2
RS485TIME[7:0] External RS-485 transceiver turn-around time delay. The value
Symbol
Symbol
AFCR1[7:5]
AFCR1[4]
AFCR1[3]
AFCR1[2]
Symbol
SAMPR[7:2]
SAMPR[1:0]
Sampling rate register bits description
RS-485 programmable turn-around time register
Advanced Feature Control Register 1 bits description
Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
All information provided in this document is subject to legal disclaimers.
Sleep RXLow. Program RX input to be edge-sensitive or level-sensitive.
RTS/CTS mapped to DTR/DSR. Switch the function of RTS/CTS to
Description
reserved
reserved
DTR/DSR.
logic 0 = RX input is level sensitive. If RX pin is LOW, the UART will not
go to sleep. Once the UART is in Sleep mode, it will wake up if RX pin
goes LOW.
logic 1 = RX input is edge sensitive. UART will go to sleep even if RX pin
is LOW, and will wake up when RX pin toggles.
logic 0 = RTS and CTS signals are used for hardware flow control
logic 1 = DTR and DSR signals are used for hardware flow control. RTS
and CTS retain their functionality.
Rev. 2 — 22 March 2011
Description
represents the bit time at the programmed baud rate.
Description
reserved
sampling rate
00 = 16
01 = 8
10 = 4
11 = reserved
SC16C850SV
© NXP B.V. 2011. All rights reserved.
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