SC16IS752IPW,112 NXP Semiconductors, SC16IS752IPW,112 Datasheet - Page 17

• Manufacturer Part Number: SC16IS752IPW,112
• Description: IC UART DUAL 12C/SPI 28TSSOP
• Manufacturer: NXP Semiconductors
• Type: IrDA or RS- 232 or RS- 485r

Specifications of SC16IS752IPW,112

• Number Of Channels: 2, DUART
• Package / Case: 28-TSSOP (0.173", 4.40mm Width)
• Features: Low Current
• Fifo's: 64 Byte
• Protocol: RS232, RS485
• Voltage - Supply: 2.5V, 3.3V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Data Rate: 5 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.3 V
• Supply Current: 6 mA
• Maximum Operating Temperature: + 95 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 2.5 V or 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-4000 - DEMO BOARD SPI/I2C TO DUAL UART568-3510 - DEMO BOARD SPI/I2C TO UART
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4016-5; 935279292112; SC16IS752IPW; SC16IS752IPW

NXP Semiconductors
SC16IS752_SC16IS762_7
Product data sheet
Figure 10
DLL and DLH must be written to in order to program the baud rate. DLL and DLH are the
least significant and most significant byte of the baud rate divisor. If DLL and DLH are both
zero, the UART is effectively disabled, as no baud clock will be generated.
Remark: The programmable baud rate generator is provided to select both the transmit
and receive clock rates.
Table 7
1.8432 MHz and 3.072 MHz, respectively.
Figure 11
Table 7.
Desired baud rate
(bit/s)
50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
56000
Fig 10. Prescaler and baud rate generator block diagram
XTAL1
XTAL2
and
shows the internal prescaler and baud rate generator circuitry.
shows the crystal clock circuit reference.
Baud rates using a 1.8432 MHz crystal
Table 8
OSCILLATOR
INTERNAL
LOGIC
show the baud rate and divisor correlation for crystal with frequency
Dual UART with I
Divisor used to generate
16 clock
2304
1536
1047
857
768
384
192
96
64
58
48
32
24
16
12
6
3
2
Rev. 07 — 19 May 2008
input clock
(DIVIDE-BY-1)
(DIVIDE-BY-4)
PRESCALER
PRESCALER
LOGIC
LOGIC
2
SC16IS752/SC16IS762
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
MCR[7] = 0
MCR[7] = 1
reference
clock
Percent error difference
between desired and actual
0
0
0.026
0.058
0
0
0
0
0
0.69
0
0
0
0
0
0
0
2.86
GENERATOR
BAUD RATE
LOGIC
© NXP B.V. 2008. All rights reserved.
002aaa233
internal
baud rate
clock for
transmitter
and receiver
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