SC16IS752IPW,112 NXP Semiconductors, SC16IS752IPW,112 Datasheet - Page 24

• Manufacturer Part Number: SC16IS752IPW,112
• Description: IC UART DUAL 12C/SPI 28TSSOP
• Manufacturer: NXP Semiconductors
• Type: IrDA or RS- 232 or RS- 485r

Specifications of SC16IS752IPW,112

• Number Of Channels: 2, DUART
• Package / Case: 28-TSSOP (0.173", 4.40mm Width)
• Features: Low Current
• Fifo's: 64 Byte
• Protocol: RS232, RS485
• Voltage - Supply: 2.5V, 3.3V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Data Rate: 5 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.3 V
• Supply Current: 6 mA
• Maximum Operating Temperature: + 95 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 2.5 V or 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-4000 - DEMO BOARD SPI/I2C TO DUAL UART568-3510 - DEMO BOARD SPI/I2C TO UART
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4016-5; 935279292112; SC16IS752IPW; SC16IS752IPW

NXP Semiconductors
SC16IS752_SC16IS762_7
Product data sheet
8.5 Interrupt Identification Register (IIR)
8.6 Line Control Register (LCR)
The IIR is a read-only 8-bit register which provides the source of the interrupt in a
prioritized manner.
Table 13.
Table 14.
[1]
This register controls the data communication format. The word length, number of stop
bits, and parity type are selected by writing the appropriate bits to the LCR.
shows the Line Control Register bit settings.
Table 15.
Bit
7:6
5:1
0
Priority
level
1
2
2
3
4
5
6
7
Bit
7
6
Modem interrupt status must be read via MSR register and GPIO interrupt status must be read via IOState
register.
Symbol
IIR[7:6]
IIR[5:1]
IIR[0]
Symbol
LCR[7]
LCR[6]
Interrupt Identification Register bits description
Interrupt source
IIR[5]
0
0
0
0
0
1
0
1
Line Control Register bits description
Table 13
IIR[4]
0
0
0
0
0
1
1
0
Dual UART with I
Description
Mirror the contents of FCR[0].
5-bit encoded interrupt. See
Interrupt status.
Description
Divisor latch enable.
Break control bit. When enabled, the Break control bit causes a break
condition to be transmitted (the TX output is forced to a logic 0 state).
This condition exists until disabled by setting LCR[6] to a logic 0.
Rev. 07 — 19 May 2008
logic 0 = an interrupt is pending
logic 1 = no interrupt is pending
logic 0 = divisor latch disabled (normal default condition)
logic 1 = divisor latch enabled
logic 0 = no TX break condition (normal default condition)
logic 1 = forces the transmitter output (TX) to a logic 0 to alert the
communication terminal to a line break condition
IIR[3]
0
1
0
0
0
0
0
0
shows Interrupt Identification Register bit settings.
IIR[2]
1
1
1
0
0
0
0
0
2
SC16IS752/SC16IS762
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
IIR[1]
1
0
0
1
0
0
0
0
Table
IIR[0]
0
0
0
0
0
0
0
0
14.
Source of the interrupt
Receive Line Status error
Receiver time-out interrupt
RHR interrupt
THR interrupt
modem interrupt
input pin change of state
received Xoff signal/special
character
CTS, RTS change of state
from active (LOW) to
inactive (HIGH)
© NXP B.V. 2008. All rights reserved.
Table 15
[1]
24 of 59
[1]