PCA9541APW/01 NXP Semiconductors, PCA9541APW/01 Datasheet - Page 16

• Manufacturer Part Number: PCA9541APW/01
• Manufacturer: NXP Semiconductors

Specifications of PCA9541APW/01

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
Table 13.
Table 14.
Legend: * default value
PCA9541A_3
Product data sheet
Bit
7
6
5
4
3
NMYTEST
7
Symbol
NMYTEST
MYTEST
-
-
BUSLOST
Register 2 - Interrupt Status register (B1:B0 = 10b) bit allocation
Register 2 - Interrupt Status (ISTAT) register bit description
8.4.3 Downstream interrupt
8.4.4 Functional test interrupt
8.4.5 Register 2: Interrupt Status Register (B1:B0 = 10b)
MYTEST
[2]
[4]
[2]
6
An interrupt can also be generated by a downstream device by asserting the INT_IN pin
LOW. When INT_IN is asserted LOW and if both INTINMSK bits are not set to ‘1’ by either
master, INT0 and INT1 both go LOW.
By setting the INTINMSK bit to ‘1’ by a master and/or the INTINMSK bit to ‘1’ by the other
master, the interrupt(s) is (are) masked and the corresponding masked channel(s) does
(do) not receive an interrupt (INT0 and/or INT1 line does (do) not go LOW).
A master can send an interrupt to itself to test its own INT wire or send an interrupt to the
other master to test its INT line. This is done by:
Setting the TESTON and/or NTESTON bits to ‘0’ by a master will clear the interrupt(s).
Remark: Interrupt outputs have an open-drain structure. Interrupt input does not have any
internal pull-up resistor and must not be left floating (that is, pulled HIGH to V
resistor) in order to avoid any undesired interrupt conditions.
The Interrupt Status Register for both the masters is identical and is described below.
Nevertheless, there are physically 2 internal Interrupt Registers, one for each upstream
channel.
When Master 0 reads this register, the internal Interrupt Register 0 will be accessed.
When Master 1 reads this register, the internal Interrupt Register 1 will be accessed.
Access Value
R only
R only
R only
R only
R only
•
•
setting the TESTON bit to ‘1’ to test its own INT line
setting the NTESTON bit to ‘1’ to test the other master INT line
5
0
0*
1
0*
1
0*
0*
0*
1
[1]
Description
no interrupt generated due to NTESTON bit from the other master
(NTESTON = 0 from the other master)
interrupt generated due to TESTON bit from the other master
(NTESTON = 1 from the other master)
no interrupt generated by TESTON bit (TESTON = 0)
interrupt generated by TESTON bit (TESTON = 1)
not used
not used
no interrupt generated to the previous master when switching to the new one
is initiated
interrupt generated to the previous master when switching to the new one is
initiated
4
0
Rev. 03 — 16 July 2009
2-to-1 I
BUSLOST
2
C-bus master selector with interrupt logic and reset
3
BUSOK
2
[3]
[3]
BUSINIT
[3]
[3]
PCA9541A
1
© NXP B.V. 2009. All rights reserved.
DD
INTIN
through
0
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