SC16C654BIBS,528 NXP Semiconductors, SC16C654BIBS,528 Datasheet - Page 27

• Manufacturer Part Number: SC16C654BIBS,528
• Description: IC QUAD UART 64BYTE 48HVQFN
• Manufacturer: NXP Semiconductors

Specifications of SC16C654BIBS,528

• Features: False-start Bit Detection
• Number Of Channels: 4, QUART
• Fifo's: 64 Byte
• Voltage - Supply: 2.5V, 3.3V, 5V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935279073528; SC16C654BIBS-F; SC16C654BIBS-F

Philips Semiconductors
9397 750 14965
Product data sheet
7.3.1.1 Mode 0 (FCR bit 3 = 0)
7.3.1.2 Mode 1 (FCR bit 3 = 1)
7.3.1 DMA mode
7.3.2 FIFO mode
7.3 FIFO Control Register (FCR)
This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO
trigger levels, and select the DMA mode.
Set and enable the interrupt for each single transmit or receive operation, and is similar to
the 16C454 mode. Transmit Ready (TXRDY) will go to a logic 0 whenever an empty
transmit space is available in the Transmit Holding Register (THR). Receive Ready
(RXRDY) will go to a logic 0 whenever the Receive Holding Register (RHR) is loaded with
a character.
Set and enable the interrupt in a block mode operation. The transmit interrupt is set when
the transmit FIFO is below the programmed trigger level. TXRDY remains a logic 0 as long
as one empty FIFO location is available. The receive interrupt is set when the receive
FIFO fills to the programmed trigger level. However, the FIFO continues to fill regardless
of the programmed level until the FIFO is full. RXRDY remains a logic 0 as long as the
FIFO fill level is above the programmed trigger level.
Table 10:
Bit
7:6
5:4
3
Symbol
FCR[7] (MSB),
FCR[6] (LSB)
FCR[5] (MSB),
FCR[4] (LSB)
FCR[3]
FIFO Control Register bits description
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
Rev. 02 — 20 June 2005
Description
RCVR trigger. These bits are used to set the trigger level for the receive
FIFO interrupt.
An interrupt is generated when the number of characters in the FIFO
equals the programmed trigger level. However, the FIFO will continue to
be loaded until it is full. Refer to
TX trigger.
These bits are used to set the trigger level for the transmit FIFO
interrupt. The SC16C654B/654DB will issue a transmit empty interrupt
when the number of characters in FIFO drops below the selected trigger
level. Refer to
DMA mode select.
Transmit operation in mode ‘0’: When the SC16C654B/654DB is in
the 16C454 mode (FIFOs disabled; FCR[0] = logic 0) or in the FIFO
mode (FIFOs enabled; FCR[0] = logic 1; FCR[3] = logic 0), and when
there are no characters in the transmit FIFO or transmit holding register,
the TXRDY pin will be a logic 0. Once active, the TXRDY pin will go to a
logic 1 after the first character is loaded into the transmit holding
register.
Receive operation in mode ‘0’: When the SC16C654B/654DB is in
mode ‘0’ (FCR[0] = logic 0), or in the FIFO mode (FCR[0] = logic 1;
FCR[3] = logic 0) and there is at least one character in the receive FIFO,
the RXRDY pin will be a logic 0. Once active, the RXRDY pin will go to a
logic 1 when there are no more characters in the receiver.
logic 0 = set DMA mode ‘0’ (normal default condition)
logic 1 = set DMA mode ‘1’
Table
12.
SC16C654B/654DB
Table
11.
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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