SC16C654BIBS,528 NXP Semiconductors, SC16C654BIBS,528 Datasheet - Page 35

• Manufacturer Part Number: SC16C654BIBS,528
• Description: IC QUAD UART 64BYTE 48HVQFN
• Manufacturer: NXP Semiconductors

Specifications of SC16C654BIBS,528

• Features: False-start Bit Detection
• Number Of Channels: 4, QUART
• Fifo's: 64 Byte
• Voltage - Supply: 2.5V, 3.3V, 5V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935279073528; SC16C654BIBS-F; SC16C654BIBS-F

Philips Semiconductors
9397 750 14965
Product data sheet
7.10 Enhanced Feature Register (EFR)
7.9 Scratchpad Register (SPR)
The SC16C654B/654DB provides a temporary data register to store 8 bits of user
information.
Enhanced features are enabled or disabled using this register.
Bits 0 through 4 provide single or dual character software flow control selection. When the
Xon1 and Xon2 and/or Xoff1 and Xoff2 modes are selected, the double 8-bit words are
concatenated into two sequential numbers.
Table 22:
Bit
7
6
5
4
3:0
Symbol
EFR[7]
EFR[6]
EFR[5]
EFR[4]
EFR[3:0]
Enhanced Feature Register bits description
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
Description
Auto CTS. Automatic CTS Flow Control.
Auto RTS. Automatic RTS may be used for hardware flow control by enabling
EFR[6]. When Auto RTS is selected, an interrupt will be generated when the
receive FIFO is filled to the programmed trigger level and RTS will go to a
logic 1 at the next trigger level. RTS will return to a logic 0 when data is
unloaded below the next lower trigger level. The state of this register bit
changes with the status of the hardware flow control. RTS functions normally
when hardware flow control is disabled.
Special Character Detect.
Enhanced function control bit. The content of IER[7:4], ISR[5:4], FCR[5:4],
and MCR[7:5] can be modified and latched. After modifying any bits in the
enhanced registers, EFR[4] can be set to a logic 0 to latch the new values.
This feature prevents existing software from altering or overwriting the
SC16C654B/654DB enhanced functions.
Cont-3:0 Tx, Rx control. Logic 0 or cleared is the default condition.
Combinations of software flow control can be selected by programming these
bits. See
logic 0 = automatic CTS flow control is disabled (normal default condition)
logic 1 = enable Automatic CTS flow control. Transmission will stop when
CTS goes to a logical 1. Transmission will resume when the CTS pin
returns to a logical 0.
logic 0 = automatic RTS flow control is disabled (normal default condition)
logic 1 = enable Automatic RTS flow control
logic 0 = special character detect disabled (normal default condition)
logic 1 = special character detect enabled. The SC16C654B/654DB
compares each incoming receive character with Xoff2 data. If a match
exists, the received data will be transferred to FIFO and ISR[4] will be set to
indicate detection of special character. Bit-0 in the X-registers corresponds
with the LSB bit for the receive character. When this feature is enabled, the
normal software flow control must be disabled (EFR[3:0] must be set to a
logic 0).
logic 0 = disable (normal default condition)
logic 1 = enable
Rev. 02 — 20 June 2005
Table
23.
SC16C654B/654DB
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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