SC16C554BIBS,557 NXP Semiconductors, SC16C554BIBS,557 Datasheet - Page 15

• Manufacturer Part Number: SC16C554BIBS,557
• Description: IC UART QUAD SOT778-3
• Manufacturer: NXP Semiconductors

Specifications of SC16C554BIBS,557

• Number Of Channels: 4, QUART
• Fifo's: 16 Byte
• Voltage - Supply: 2.5V, 3.3V, 5V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935279072557; SC16C554BIBS; SC16C554BIBS

NXP Semiconductors
6. Functional description
SC16C554B_554DB
Product data sheet
The SC16C554B/554DB provides serial asynchronous receive data synchronization,
parallel-to-serial and serial-to-parallel data conversions for both the transmitter and
receiver sections. These functions are necessary for converting the serial data stream into
parallel data that is required with digital data systems. Synchronization for the serial data
stream is accomplished by adding start and stop bits to the transmit data to form a data
character. Data integrity is insured by attaching a parity bit to the data character. The
parity bit is checked by the receiver for any transmission bit errors. The electronic circuitry
to provide all these functions is fairly complex, especially when manufactured on a single
integrated silicon chip. The SC16C554B/554DB represents such an integration with
greatly enhanced features. The SC16C554B/554DB is fabricated with an advanced
CMOS process to achieve low drain power and high speed requirements.
The SC16C554B/554DB is an upward solution that provides 16 bytes of transmit and
receive FIFO memory, instead of none in the 16C454. The SC16C554B/554DB is
designed to work with high speed modems and shared network environments that require
fast data processing time. Increased performance is realized in the SC16C554B/554DB
by the larger transmit and receive FIFOs. This allows the external processor to handle
more networking tasks within a given time. In addition, the four selectable levels of FIFO
trigger interrupt is uniquely provided for maximum data throughput performance,
especially when operating in a multi-channel environment. The combination of the above
greatly reduces the bandwidth requirement of the external controlling CPU, increases
performance, and reduces power consumption.
The SC16C554B/554DBAI68 combines the package interface modes of the 16C454/554
and 68C454/554 series on a single integrated chip. The 16 mode interface is designed to
operate with the Intel-type of microprocessor bus, while the 68 mode is intended to
operate with Motorola and other popular microprocessors. Following a reset, the
SC16C554B/554DBAI68 is downward compatible with the 16C454/554 or the
68C454/554, dependent on the state of the interface mode selection pin, 16/68.
The SC16C554B/554DB is capable of operation to 1.5 Mbit/s with a 24 MHz crystal and
up to 5 Mbit/s with an external clock input (at 3.3 V and 5 V; at 2.5 V the maximum speed
is 3 Mbit/s).
The rich feature set of the SC16C554B/554DB is available through internal registers.
Selectable receive FIFO trigger levels, selectable transmit and receive baud rates, and
modem interface controls are all standard features. In the 16 mode, INTSEL and MCR[3]
can be configured to provide a software controlled or continuous interrupt capability. Due
to pin limitations of the 64-pin package, this feature is offered by two different LQFP64
packages. The SC16C554DB operates in the continuous interrupt enable mode by
bonding INTSEL to V
by bonding INTSEL to GND internally.
All information provided in this document is subject to legal disclaimers.
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs
CC
Rev. 4 — 8 June 2010
internally. The SC16C554B operates in conjunction with MCR[3]
SC16C554B/554DB
© NXP B.V. 2010. All rights reserved.
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