MC68HC705C8ACS Motorola, MC68HC705C8ACS Datasheet

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MC68HC705C8ACS

Manufacturer Part Number
MC68HC705C8ACS
Description
HCMOS 8-bit microcontroller unit
Manufacturer
Motorola
Datasheet

Specifications of MC68HC705C8ACS

Case
DIP-40L
MC68HC705C8A
MC68HSC705C8A
Technical Data
M68HC05
Microcontrollers
MC68HC705C8A/D
Rev. 3, 3/2002
WWW.MOTOROLA.COM/SEMICONDUCTORS

Related parts for MC68HC705C8ACS

MC68HC705C8ACS Summary of contents

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... M68HC05 Microcontrollers WWW.MOTOROLA.COM/SEMICONDUCTORS MC68HC705C8A MC68HSC705C8A Technical Data MC68HC705C8A/D Rev. 3, 3/2002 ...

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...

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... The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location. Motorola and the Stylized M Logo are registered trademarks of Motorola, Inc. DigitalDNA is a trademark of Motorola, Inc. http://www.motorola.com/semiconductors/ © Motorola, Inc., 2002 ...

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... Quad Flat Pack (QFP) March, 2002 3 drawing from Case #824E to Case #824A Revision History Description — Added description of programming voltage ) pin 1.7 1.7.11 Port D I/O Pins (PD7 and — Updated Motorola contact information — Corrected case outline Page Number( 192 195 ...

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... Section 10. Serial Communications Interface (SCI 121 Section 11. Serial Peripheral Interface (SPI 139 Section 12. Instruction Set . . . . . . . . . . . . . . . . . . . . . . . 153 Section 13. Electrical Specifications . . . . . . . . . . . . . . 171 Section 14. Mechanical Specifications . . . . . . . . . . . . . 191 Section 15. Ordering Information . . . . . . . . . . . . . . . . . 199 Appendix A. MC68HSC705C8A . . . . . . . . . . . . . . . . . . . 201 Index 211 MC68HC705C8A — Rev. 3 MOTOROLA List of Sections List of Sections Technical Data 5 ...

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... List of Sections Technical Data 6 List of Sections MC68HC705C8A — Rev. 3 MOTOROLA ...

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... MC68HC705C8A — Rev. 3 MOTOROLA Section 1. General Description Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Programmable Options Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 V and OSC1 and OSC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 External Reset Pin (RESET .32 External Interrupt Request Pin (IRQ) ...

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... Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Arithmetic/Logic Unit (ALU Section 4. Interrupts Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Software Interrupt External Interrupt (IRQ Port B Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Capture/Compare Timer Interrupts . . . . . . . . . . . . . . . . . . .55 SCI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 SPI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Section 5. Resets Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table of Contents MC68HC705C8A — Rev. 3 MOTOROLA ...

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... MC68HC705C8A — Rev. 3 MOTOROLA Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Power-On Reset (POR External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Programmable and Non-Programmable COP Watchdog Resets . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Clock Monitor Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Section 6. Low-Power Modes Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 SCI During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 SPI During Stop Mode ...

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... Preprogramming Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 PROM Programming Routines . . . . . . . . . . . . . . . . . . . . . . . . 111 Program and Verify PROM 111 Verify PROM Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 Secure PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Secure PROM and Verify . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Secure PROM and Dump 113 Load Program into RAM and Execute . . . . . . . . . . . . . . . . 114 Table of Contents MC68HC705C8A — Rev. 3 MOTOROLA ...

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... MC68HC705C8A — Rev. 3 MOTOROLA Execute Program in RAM 115 Dump PROM Contents .115 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Mask Option Register 117 Mask Option Register 118 EPROM Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Section 10. Serial Communications Interface (SCI) Contents ...

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... Indexed, 8-Bit Offset 156 Indexed, 16-Bit Offset 156 Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Register/Memory Instructions .158 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . 159 Jump/Branch Instructions 160 Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . .162 Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Table of Contents MC68HC705C8A — Rev. 3 MOTOROLA ...

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... Serial Peripheral Interface (SPI) Timing . . . . . . . . . . 187 14.1 14.2 14.3 14.4 14.5 14.6 14.7 14.8 MC68HC705C8A — Rev. 3 MOTOROLA Section 13. Electrical Specifications Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Operating Temperature Range 173 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Power Considerations 174 5.0-Volt DC Electrical Characteristics .175 3.3-Volt DC Electrical Characteristics . . . . . . . . . . . . . . . . . .176 5 ...

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... High-Speed DC Electrical Characteristics .202 3.3-Volt High-Speed DC Electrical Characteristics . . . . . . . . 203 5.0-Volt High-Speed Control Timing . . . . . . . . . . . . . . . . . . . . 204 3.3-Volt High-Speed Control Timing . . . . . . . . . . . . . . . . . . . . 204 5.0-Volt High-Speed SPI Timing . . . . . . . . . . . . . . . . . . . . . . 205 3.3-Volt High-Speed SPI Timing .207 Ordering Information 209 Index Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 Table of Contents MC68HC705C8A — Rev. 3 MOTOROLA ...

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... MC68HC705C8A — Rev. 3 MOTOROLA Title Option Register (Option MC68HC705C8A Block Diagram . . . . . . . . . . . . . . . . . . . . . 25 40-Pin PDIP/Cerdip Pin Assignments . . . . . . . . . . . . . . . . . 26 44-Lead PLCC/CLCC Pin Assignments . . . . . . . . . . . . . . . . 27 44-Pin QFP Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . .27 42-Pin SDIP Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . 28 Bypassing Layout Recommendation . . . . . . . . . . . . . . . . . . 29 Crystal Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2-Pin Ceramic Resonator Connections ...

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... Timer Register Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Alternate Timer Register Reads . . . . . . . . . . . . . . . . . . . . . . 99 Alternate Timer Registers (ATRH and ATRL Input Capture Registers (ICRH and ICRL 100 Output Compare Registers (OCRH and OCRL .101 EPROM/OTPROM Programming Flowchart . . . . . . . . . . . 105 PROM Programming Circuit . . . . . . . . . . . . . . . . . . . . . . . . 106 List of Figures Page MC68HC705C8A — Rev. 3 MOTOROLA ...

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... MC68HC705C8A — Rev. 3 MOTOROLA Title Program Register (PROG 109 Option Register (Option 116 Mask Option Register 1 (MOR1 117 Mask Option Register 2 (MOR2 118 SCI Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 SCI Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 SCI Transmitter I/O Register Summary . . . . . . . . . . . . . . . 125 SCI Receiver ...

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... MC68HC705C8AP Package Dimensions (Case #711 192 MC68HC705C8AS Package Dimensions (Case #734A .193 MC68HC705C8AFN Package Dimensions (Case #777 194 MC68HC705C8AFS Package Dimensions (Case #777B .195 MC68HC705C8AFB Package Dimensions (Case #824A .196 MC68HC705C8AB Package Dimensions (Case #858 197 List of Figures Page MC68HC705C8A — Rev. 3 MOTOROLA ...

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... MC68HC705C8A — Rev. 3 MOTOROLA Title Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Reset/Interrupt Vector Addresses . . . . . . . . . . . . . . . . . . . . . 57 Programmable COP Timeout Period Selection . . . . . . . . . . . 66 Port A Pin Functions Port B Pin Functions Port C Pin Functions MC68HC05PGMR PCB Reference Designators . . . . . . . . .104 PROM Programming Routines . . . . . . . . . . . . . . . . . . . . . . .108 Baud Rate Generator Clock Prescaling ...

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... List of Tables Table A-1 A-2 Technical Data 20 Title Programmable COP Timeout Period Selection . . . . . . . . . . . 202 MC68HSC705C8A Order Numbers . . . . . . . . . . . . . . . . . . . . 209 List of Tables Page MC68HC705C8A — Rev. 3 MOTOROLA ...

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... MC68HC705C8A — Rev. 3 MOTOROLA Section 1. General Description Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Programmable Options Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 V and OSC1 and OSC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Crystal Resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Ceramic Resonator ...

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... High current drive on pin C7 (PC7) 24 bidirectional I/O lines and 7 input-only lines Serial communications interface (SCI) system Serial peripheral interface (SPI) system Bootstrap capability Power-saving stop, wait, and data-retention modes Single 3.0-volt to 5.5-volt supply (2-volt data-retention mode) Fully static operation General Description MC68HC705C8A — Rev. 3 MOTOROLA ...

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... Address: Read: Write: Reset security feature is absolutely secure. However, Motorola’s strategy is to make reading or copying the PROM difficult for unauthorized users. MC68HC705C8A — Rev. 3 MOTOROLA Software-programmable external interrupt sensitivity Bidirectional RESET pin Specifications. Enabling of port B pullup devices (see ...

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... Provides 96 bytes of PROM at location $0100 Bootloader disabled; MCU operates only in single-chip mode 0 = Security off; bootloader can be enabled 1 = IRQ pin is both negative edge- and level-sensitive IRQ pin is negative edge-sensitive only. shows the structure of the MC68HC705C8A. General Description MC68HC705C8A — Rev. 3 MOTOROLA ...

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... POWER Port B pins also function as external interrupts. † PC7 has a high current sink and source capability. Figure 1-2. MC68HC705C8A Block Diagram MC68HC705C8A — Rev. 3 MOTOROLA PROGRAM REGISTER (144 BYTES CONFIGURABLE) OPTION REGISTER RAM — 176 BYTES (304 BYTES MAXIMUM) BOOT ROM — 240 BYTES ...

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... PB0 12 PB1 13 PB2 14 PB3 15 PB4 16 PB5 17 PB6 18 PB7 Figure 1-3. 40-Pin PDIP/Cerdip Pin Assignments General Description Figure 1-3, 1- OSC1 38 OSC2 37 TCAP 36 PD7 35 TCMP 34 PD5/SS 33 PD4/SCK 32 PD3/MOSI 31 PD2/MISO 30 PD1/TDO 29 PD0/RDI 28 PC0 27 PC1 26 PC2 25 PC3 24 PC4 23 PC5 22 PC6 21 PC7 MC68HC705C8A — Rev. 3 MOTOROLA ...

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... MC68HC705C8A — Rev. 3 MOTOROLA PA5 7 PA4 8 9 PA3 PA2 10 11 PA1 PA0 12 PB0 13 14 PB1 PB2 15 PB3 16 PB4 17 Figure 1-4. 44-Lead PLCC/CLCC Pin Assignments PD7 34 TCAP 35 OSC2 36 OSC1 RESET 41 IRQ PA7 Figure 1-5. 44-Pin QFP Pin Assignments General Description General Description ...

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... PB2 14 29 PB3 PB4 17 26 PB5 18 25 PB6 PB7 Figure 1-6. 42-Pin SDIP Pin Assignments General Description V DD OSC1 OSC2 TCAP PD7 TCMP PD5/SS PD4/SCK PD3/MOSI PD2/MISO PD1/TDO PD0/RDI PC0 PC1 PC2 NC PC3 PC4 PC5 PC6 PC7 MC68HC705C8A — Rev. 3 MOTOROLA ...

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... V PP This pin provides the programming voltage to the EPROM array. For normal operation, V NOTE: Connecting the V result in damage to the MCU. MC68HC705C8A — Rev. 3 MOTOROLA and V are the power supply and ground pins. The MCU operates SS 1-7. shuld be tied pin (programming voltage ...

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... General Description . The MCU divides the OSC MCU OSC2 OSC1 10 M XTAL 2 MHz Starting value only. Follow crystal supplier’s recommendations regarding component values that will provide reliable startup and maximum stability. Figure 1-8. Crystal Connections MC68HC705C8A — Rev. 3 MOTOROLA ...

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... To minimize output distortion, mount the resonator and capacitors as close as possible to the pins. NOTE: The bus frequency (f (f OSC period. MC68HC705C8A — Rev. 3 MOTOROLA Figure 1-9 for a 2-pin for a 3-pin ceramic OSC1 CERAMIC RESONATOR Figure 1-10. 3-Pin Ceramic Resonator ...

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... See Timer. Technical Data 32 Figure 1-11 shows one-half the external frequency (f OP OSC Section 5. 4.3.2 External Interrupt (IRQ). Section 8. Capture/Compare General Description MCU EXTERNAL CMOS CLOCK Figure 1-11. External Clock ) while OSC period. Resets. MC68HC705C8A — Rev. 3 MOTOROLA ...

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... See 1.7.11 Port D I/O Pins (PD7 and PD5–PD0) These seven lines comprise port D, a fixed input port. All special functions that are enabled (SPI and SCI) affect this port. See MC68HC705C8A — Rev. 3 MOTOROLA Section 8. Capture/Compare 7.5 Port C. General Description ...

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... General Description Technical Data 34 General Description MC68HC705C8A — Rev. 3 MOTOROLA ...

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... I/O registers are memory-mapped so that the CPU can access their locations in the same way that it accesses all other memory locations. The shared stack area is used during processing of an interrupt or MC68HC705C8A — Rev. 3 MOTOROLA Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Memory Map Input/Output (I/ RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 EPROM/OTPROM (PROM) ...

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... Figure 2-2 Table 2-1. Memory Configurations RAM0 RAM1 Memory for more information. Table 2-1. See 9.5.1 Option RAM Bytes PROM Bytes 176 7744 208 7696 272 7648 304 7600 MC68HC705C8A — Rev. 3 MOTOROLA ...

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... OTPROM (see Section 9. EPROM/OTPROM 2.7 Bootloader ROM The 240 bytes at addresses $1F00–$1FEF are reserved ROM addresses that contain the instructions for the bootloader functions. See Section 9. EPROM/OTPROM MC68HC705C8A — Rev. 3 MOTOROLA (PROM). (PROM). Memory Memory EPROM/OTPROM (PROM) Table 2-1) ...

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... TIMER REGISTER (LOW) $0019 $001A $001B $001C COP RESET REGISTER $001D COP CONTROL REGISTER $001E UNUSED $001F RESERVED $1FF2 RESERVED $1FF3 $1FF4 $1FF5 $1FF6 $1FF7 $1FF8 $1FF9 $1FFA $1FFB $1FFC $1FFD RESET VECTOR (HIGH) $1FFE RESET VECTOR (LOW) $1FFF MC68HC705C8A — Rev. 3 MOTOROLA ...

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... Register (DDRB) See page 82. Port C Data Direction $0006 (DDRC) See page 86. $0007 Unimplemented $0008 Unimplemented $0009 Unimplemented Figure 2-2. I/O Register Summary (Sheet MC68HC705C8A — Rev. 3 MOTOROLA Bit Read: PA7 PA6 PA5 Write: Reset: Read: PB7 PB6 PB5 Write: Reset: ...

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... Read: ICIE OCIE TOIE Write: Reset Unimplemented U = Unaffected Memory CPOL CPHA SPR1 Bit 4 Bit 3 BIt 2 Bit 1 SCR2 SCR1 WAKE U U ILIE TE RE RWU IDLE Bit 4 Bit 3 Bit 2 Bit IEDG MC68HC705C8A — Rev. 3 MOTOROLA Bit 0 SPR0 U Bit 0 SCR0 U SBK 0 U Bit 0 OLVL 0 ...

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... Timer Register Low $0019 (TRL) See page 97. Alternate Timer Register $001A High (ATRH) See page 99. Alternate Timer Register $001B Low (ATRL) See page 99. Figure 2-2. I/O Register Summary (Sheet MC68HC705C8A — Rev. 3 MOTOROLA Bit Read: ICF OCF TOF Write: Reset Read: Bit 15 ...

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... PBPU7 PBPU6 PBPU5 PBPU4 Write: Reset: Unaffected by reset Read: Write: Reset: Unaffected by reset = Unimplemented U = Unaffected Memory LAT Bit 4 Bit 3 Bit 2 Bit CME PCOPE CM1 SEC IRQ * PBPU3 PBPU2 PBPU1 MC68HC705C8A — Rev. 3 MOTOROLA Bit 0 PGM 0 Bit 0 U CM0 PBPU0/ COPC NCOPE ...

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... Introduction This section describes the central processor unit (CPU) registers. MC68HC705C8A — Rev. 3 MOTOROLA Section 3. Central Processor Unit (CPU) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Arithmetic/Logic Unit (ALU ...

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... Bit Bit HALF-CARRY FLAG INTERRUPT MASK NEGATIVE FLAG ZERO FLAG CARRY/BORROW FLAG Figure 3-1. Programming Model Central Processor Unit (CPU Bit 0 ACCUMULATOR ( Bit 0 INDEX REGISTER ( Bit 0 STACK POINTER (SP Bit 0 PROGRAM COUNTER (PC Bit CONDITION CODE REGISTER (CCR) MC68HC705C8A — Rev. 3 MOTOROLA ...

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... See Offset, and indexed addressing. The 8-bit index register also can serve as a temporary data storage location. Read: Write: Reset: MC68HC705C8A — Rev. 3 MOTOROLA Figure 3-2 Bit Unaffected by reset Figure 3-2. Accumulator (A) Figure 3-3 to determine the conditional address of 12 ...

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... Bit 12 11 Read: Write: Reset: Technical Data 46 Figure 3 Figure 3-4. Stack Pointer (SP Loaded with reset vector from $1FFE and $1FFF Figure 3-5. Program Counter (PC) Central Processor Unit (CPU 13-bit register that Figure 3 13-bit register that MC68HC705C8A — Rev. 3 MOTOROLA Bit 0 1 Bit 0 ...

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... A return-from-interrupt (RTI) instruction pulls the CPU registers from the stack, restoring the interrupt mask to its cleared state. After a reset, the interrupt mask is set and can be cleared only by a CLI, STOP, or WAIT instruction. MC68HC705C8A — Rev. 3 MOTOROLA Bit ...

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... Multiplication is not performed as a discrete operation but as a chain of addition and shift operations within the ALU. The multiply instruction requires 11 internal clock cycles to complete this chain of operations. Technical Data 48 Central Processor Unit (CPU) MC68HC705C8A — Rev. 3 MOTOROLA ...

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... Introduction This section describes how interrupts temporarily change the normal processing sequence. MC68HC705C8A — Rev. 3 MOTOROLA Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Software Interrupt External Interrupt (IRQ Port B Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Capture/Compare Timer Interrupts . . . . . . . . . . . . . . . . . . .55 SCI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 SPI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Interrupts Section 4 ...

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... SCI transmit data register empty – SCI transmission complete – SCI receive data register full – SCI receiver overrun – SCI receiver input idle Serial peripheral interface (SPI): – SPI transmission complete – SPI mode fault – SPI overrun Interrupts MC68HC705C8A — Rev. 3 MOTOROLA ...

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... The internal interrupt latch is cleared in the first part of the interrupt service routine. Therefore, a new external interrupt pulse could be latched and serviced as soon as the I bit is cleared. If the IRQ pin is not in use, connect it to the V MC68HC705C8A — Rev. 3 MOTOROLA IRQ latch I bit in the CCR Figure 4-1 shows an external interrupt functional diagram. ...

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... ILIL cycles. CYC t ILIH Figure 4-2. External Interrupt Timing Interrupts EXTERNAL INTERRUPT REQUEST POR INTERNAL RESET (COP) EXTERNAL RESET EXTERNAL INTERRUPT BEING SERVICED (VECTOR FETCH either 125 2.1 MHz) ILIH OP cycles it takes to CYC MC68HC705C8A — Rev. 3 MOTOROLA ...

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... B external interrupt signal returns to a logic 1 and then falls again to a logic 0. Figure 4-3 MC68HC705C8A — Rev. 3 MOTOROLA The corresponding port B pullup bit (PBPUx) in mask option register 1 (MOR1) is programmed to a logic 1. The corresponding port B data direction bit (DDRBx) in data direction register B (DDRB logic 0 ...

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... PORT B PINS IRQ RESET EXTERNAL INTERRUPT VECTOR FETCH Technical Data 54 PBPU7 FROM MOR1 DATA DIRECTION REGISTER B BIT DDRB7 PORT B DATA REGISTER BIT PB7 Figure 4-3. Port B I/O Logic Interrupts V DD PB7 EXTERNAL INTERRUPT REQUEST I BIT FROM CCR MC68HC705C8A — Rev. 3 MOTOROLA ...

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... Setting the I bit in the CCR disables all SCI interrupts. • • • MC68HC705C8A — Rev. 3 MOTOROLA Transmit data register empty interrupt Transmission complete interrupt Receive data register full interrupt Receiver overrun interrupt Receiver input idle interrupt SCI Transmit Data Register Empty Interrupt — The transmit data register empty bit (TDRE) indicates that the SCI data register is ready to receive a byte for transmission ...

Page 56

... SPI Mode Fault Interrupt — The mode fault bit (MODF) in the SPI status register indicates an SPI mode error. MODF becomes set when a logic 0 occurs on the PD5/SS pin while the master bit (MSTR) in the SPI control register is set. MODF generates an interrupt request if the SPIE bit is set also. Interrupts MC68HC705C8A — Rev. 3 MOTOROLA ...

Page 57

... External interrupt interrupts interrupts interrupts The return-from-interrupt (RTI) instruction causes the CPU to recover the CPU registers from the stack as shown in MC68HC705C8A — Rev. 3 MOTOROLA Figure 4-4 interrupt vector locations as shown in Table 4-1. Reset/Interrupt Vector Addresses Local Source Mask Power-on logic ...

Page 58

... PROGRAM COUNTER (LOW BYTE) • • • Figure 4-4. Interrupt Stacking Order shows the sequence of events caused by an interrupt. Interrupts $00C0 (BOTTOM OF STACK) $00C1 $00C2 • • • • • • $00FD $00FE $00FF (TOP OF STACK) Table 4-1 for a priority MC68HC705C8A — Rev. 3 MOTOROLA ...

Page 59

... YES CCR REGISTER INSTRUCTION INSTRUCTION? INSTRUCTION? Figure 4-5. Reset and Interrupt Processing Flowchart MC68HC705C8A — Rev. 3 MOTOROLA FROM RESET I BIT IN SET? NO EXTERNAL YES CLEAR IRQ REQUEST LATCH IRQ INTERRUPT? NO YES TIMER INTERRUPT? NO YES SCI INTERRUPT? NO YES SPI INTERRUPT STACK PC CCR 2. SET I BIT 3 ...

Page 60

... Interrupts Technical Data 60 MC68HC705C8A — Rev. 3 Interrupts MOTOROLA ...

Page 61

... These conditions produce a reset: • • • • • MC68HC705C8A — Rev. 3 MOTOROLA Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Power-On Reset (POR External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Programmable and Non-Programmable COP Watchdog Resets . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Programmable COP Watchdog Reset . . . . . . . . . . . . . . .63 Non-Programmable COP Watchdog . . . . . . . . . . . . . . . . 66 Clock Monitor Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Power-on reset (POR) — ...

Page 62

... CYC , the MCU remains in the reset condition CYC . However, to guarantee that the MCU recognizes an external reset . After six t CYC . CYC Resets , the input on the RESET pin CYC after CYC MC68HC705C8A — Rev. 3 MOTOROLA ...

Page 63

... COP watchdog does not time out before the second write. PROGRAMMABLE COP WATCHDOG (MC68HC705C8 TYPE) INTERNAL CLOCK COPRST Figure 5-1. Programmable COP Watchdog Diagram MC68HC705C8A — Rev. 3 MOTOROLA Figure 5-1 COP reset register (COPRST), $001D COP control register (COPCR), $001E Figure 5- ...

Page 64

... Enables the programmable COP watchdog Controls the timeout period of the programmable COP watchdog $001E Bit COPF Unimplemented 1 = COP timeout or internal clock failure COP timeout and no internal clock failure Resets Bit Bit Unaffected Figure 5 Bit 0 CME PCOPE CM1 CM0 Unaffected MC68HC705C8A — Rev. 3 MOTOROLA ...

Page 65

... They can be cleared only by reset. Bits 7–5 — Unused Bits 7–5 always read as logic 0s. Reset clears bits 7–5. MC68HC705C8A — Rev. 3 MOTOROLA 1 = Clock monitor enabled 0 = Clock monitor disabled 1 = Programmable COP watchdog enabled 0 = Programmable COP watchdog disabled 9 ...

Page 66

... Programming the NCOPE bit in MOR2 to a logic 1 enables the non-programmable COP watchdog. See Register 2. Resets f = 2.0 MHz f = 1.0 MHz OSC OSC f = 1.0 MHz f = 0.5 MHz OP OP 32.77 ms 65.54 ms 131.07 ms 262.14 ms 524.29 ms 1.048 s 2.097 s 4.194 s 262,144 f OSC 9.5.3 Mask Option MC68HC705C8A — Rev. 3 MOTOROLA ...

Page 67

... Since STOP causes the system clocks to halt, the clock monitor issues a system reset when STOP is executed. MC68HC705C8A — Rev. 3 MOTOROLA To clear the non-programmable COP watchdog and start a new COP timeout period, write a logic 0 to bit 0 of address $1FF0. ...

Page 68

... The clock monitor would detect such a condition and force the MCU to a reset state. Clocks are not required for the MCU to reach a reset condition. They are, however, required to bring the MCU through the reset sequence and back to run condition. Technical Data 68 MC68HC705C8A — Rev. 3 Resets MOTOROLA ...

Page 69

... In stop mode, the internal oscillator is turned off, halting all internal processing including timer, serial communications interface (SCI), and master mode serial peripheral interface (SPI) operation. See MC68HC705C8A — Rev. 3 MOTOROLA Section 6. Low-Power Modes Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 SCI During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 SPI During Stop Mode ...

Page 70

... CLEAR I BIT RESET YES YES RESTART CPU CLOCK 1. FETCH RESET VECTOR SERVICE INTERRUPT: a. STACK b. SET I BIT c. VECTOR TO INTERRUPT ROUTINE Low-Power Modes NO EXTERNAL NO INTERRUPT (IRQ) YES INTERNAL TIMER INTERRUPT YES NO YES INTERNAL SCI INTERRUPT NO NO YES INTERNAL SPI INTERRUPT MC68HC705C8A — Rev. 3 MOTOROLA ...

Page 71

... MCU out of stop mode, the reset function clears and disables the COP watchdog. If the IRQ pin brings the MCU out of stop mode, the COP counter resumes counting from its suspended value after the 4064-t stabilization delay. See MC68HC705C8A — Rev. 3 MOTOROLA Figure 6-2. Low-Power Modes Low-Power Modes Stop Mode ...

Page 72

... Low-Power Modes TURN ON INTERNAL OSCILLATOR CLEAR COP COUNTER CLEAR PCOPE BIT IN COPCR END OF YES STABILIZATION DELAY? NO TURN ON INTERNAL CLOCK 1. LOAD PC WITH RESET VECTOR OR 2. SERVICE INTERRUPT: a. SAVE CPU REGISTERS ON STACK b. SET I BIT IN CCR c. LOAD PC WITH INTERRUPT VECTOR MC68HC705C8A — Rev. 3 MOTOROLA ...

Page 73

... The WAIT instruction does not affect any other registers or I/O lines. The capture/compare timer, SCI, and SPI can be enabled to allow a periodic exit from wait mode. MC68HC705C8A — Rev. 3 MOTOROLA Turns off the oscillator and the COP watchdog counter Clears the COP watchdog counter clock stabilization delay. ...

Page 74

... Stop Mode (NCOPE = 1) Flowchart Low-Power Modes TURN ON INTERNAL OSCILLATOR TURN ON COP WATCHDOG END OF YES STABILIZATION DELAY? NO CLEAR COP COUNTER TURN ON INTERNAL CLOCK 1. LOAD PC WITH RESET VECTOR OR 2. SERVICE INTERRUPT: a. SAVE CPU REGISTERS ON STACK b. SET I BIT IN CCR c. LOAD PC WITH INTERRUPT VECTOR MC68HC705C8A — Rev. 3 MOTOROLA ...

Page 75

... Drive the RESET pin to logic 0. 2. Lower V To take the MCU out of data-retention mode: 1. Return V 2. Return the RESET pin to logic 1. MC68HC705C8A — Rev. 3 MOTOROLA voltage. The RESET pin must remain low continuously DD during data-retention mode. to normal operating voltage. DD Low-Power Modes ...

Page 76

... Low-Power Modes Technical Data 76 Low-Power Modes MC68HC705C8A — Rev. 3 MOTOROLA ...

Page 77

... Introduction This section describes the programming of ports and D. MC68HC705C8A — Rev. 3 MOTOROLA Section 7. Parallel Input/Output (I/O) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Port Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Data Direction Register Port A Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Port Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Data Direction Register Port B Logic ...

Page 78

... A. Reset has no effect on port A data. Technical Data 78 $0000 Bit PA7 PA6 PA5 PA4 Unaffected by reset Figure 7-1. Port A Data Register (PORTA) Parallel Input/Output (I/O) Figure 7-1 contains a data Bit 0 PA3 PA2 PA1 PA0 MC68HC705C8A — Rev. 3 MOTOROLA ...

Page 79

... DDRA7–DDRA0 — Port A Data Direction Bits These read/write bits control port A data direction. Reset clears bits DDRA7–DDRA0. NOTE: Avoid glitches on port A pins by writing to the port A data register before changing DDRA bits from logic 0 to logic 1. MC68HC705C8A — Rev. 3 MOTOROLA $0004 Bit DDRA7 DDRA6 ...

Page 80

... A pins. Table 7-1. Port A Pin Functions Accesses to DDRA I/O Pin Mode Read/Write (1) 0 DDRA7–DDRA0 Input, Hi-Z 1 Output DDRA7–DDRA0 Parallel Input/Output (I/O) PAx Accesses to PORTA Read Write (2) Pin PA7–PA0 PA7–PA0 PA7–PA0 MC68HC705C8A — Rev. 3 MOTOROLA ...

Page 81

... Write: Reset: PB7–PB0 — Port B Data Bits These read/write bits are software programmable. Data direction of each bit is under the control of the corresponding bit in data direction register B. Reset has no effect on port B data. MC68HC705C8A — Rev. 3 MOTOROLA and 4.3.3 Port B $0001 Bit ...

Page 82

... DDRB bits from logic 0 to logic 1. Technical Data 82 $0005 Bit DDRB7 DDRB6 DDRB5 DDRB4 Figure 7-5. Data Direction Register B (DDRB Corresponding port B pin configured as output 0 = Corresponding port B pin configured as input Parallel Input/Output (I/O) Figure 7 Bit 0 DDRB3 DDRB2 DDRB1 DDRB0 MC68HC705C8A — Rev. 3 MOTOROLA ...

Page 83

... RESET WRITE $0001 READ $0001 FROM OPTION REGISTER FROM OTHER PORT B PINS IRQ RESET EXTERNAL INTERRUPT VECTOR FETCH MC68HC705C8A — Rev. 3 MOTOROLA shows the port B I/O logic. PBPU7 FROM MOR1 DATA DIRECTION REGISTER B BIT DDRB7 PORT B DATA REGISTER BIT PB7 IRQ ...

Page 84

... I/O pins change to outputs by writing to DDRB in user code as early as possible. Technical Data 84 Table 7-2. Port B Pin Functions Accesses to DDRB I/O Pin Mode Read/Write (1) 0 DDRB7–DDRB0 Input, Hi-Z 1 Output DDRB7–DDRB0 Parallel Input/Output (I/O) Accesses to PORTB Read Write (2) Pin PB7–PB0 PB7–PB0 PB7–PB0 MC68HC705C8A — Rev. 3 MOTOROLA ...

Page 85

... PC7–PC0 — Port C Data Bits These read/write bits are software programmable. Data direction of each bit is under the control of the corresponding bit in data direction register C. PC7 has a high current sink and source capability. Reset has no effect on port C data. MC68HC705C8A — Rev. 3 MOTOROLA $0002 Bit ...

Page 86

... DDRC bits from logic 0 to logic 1. Technical Data 86 $0006 Bit DDRC7 DDRC6 DDRC5 DDRC4 Figure 7-8. Data Direction Register C (DDRC Corresponding port C pin configured as output 0 = Corresponding port C pin configured as input Parallel Input/Output (I/O) Figure 7 Bit 0 DDRC3 DDRC2 DDRC1 DDRC0 MC68HC705C8A — Rev. 3 MOTOROLA ...

Page 87

... Writing affects data register but does not affect input. NOTE: To avoid excessive current draw, tie all unused input pins change I/O pins to outputs by writing to DDRC in user code as early as possible. MC68HC705C8A — Rev. 3 MOTOROLA shows port C I/O logic. READ $0006 WRITE $0006 DATA DIRECTION REGISTER C ...

Page 88

... PD1 and PD0 pins. Address: Read: Write: Reset: Technical Data 88 $0003 Bit PD7 SS SCK Unaffected by reset = Unimplemented Figure 7-10. Port D Fixed Input Register (PORTD) Parallel Input/Output (I/ Bit 0 MOSI MISO TDO RDI MC68HC705C8A — Rev. 3 MOTOROLA ...

Page 89

... Software can read the value in the counter at any time without affecting the counter sequence. MC68HC705C8A — Rev. 3 MOTOROLA Section 8. Capture/Compare Timer Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Output Compare ...

Page 90

... TRL ($0019) 16-BIT COUNTER 16-BIT COMPARATOR OCRH ($0016) OCRL ($0017) TIMER STATUS REGISTER INTERNAL DATA BUS Figure 8-1. Timer Block Diagram Capture/Compare Timer ATRH ($001A) ATRL ($001B) 4 INTERNAL CLOCK (XTAL 2) PIN CONTROL TCMP LOGIC TIMER INTERRUPT REQUEST $0013 MC68HC705C8A — Rev. 3 MOTOROLA ...

Page 91

... Timer Register Low $0019 (TRL) See page 97. Alternate Timer Register $001A High (ATRH) See page 99. Alternate Timer Register $001B Low (ATRL) See page 99. Figure 8-2. Timer I/O Register Summary MC68HC705C8A — Rev. 3 MOTOROLA Bit Read: ICIE OCIE TOIE Write: Reset Read: ...

Page 92

... INPUT CAPTURE REGISTER HIGH $0014 TIMER CONTROL REGISTER $0012 Figure 8-3. Input Capture Operation Capture/Compare Timer Figure 8-3 shows the logic of the $0019 TIMER REGISTER LOW INPUT CAPTURE REGISTER LOW $0015 TIMER INTERRUPT REQUEST TIMER STATUS REGISTER $0013 MC68HC705C8A — Rev. 3 MOTOROLA ...

Page 93

... TCMP pin. Figure 8-4 15 COUNTER HIGH BYTE 15 OUTPUT COMPARE REGISTER HIGH $0016 TIMER STATUS REGISTER MC68HC705C8A — Rev. 3 MOTOROLA shows the logic of the output compare function. COUNTER LOW BYTE 16-BIT COMPARATOR 8 7 OUTPUT COMPARE REGISTER LOW $0017 $0012 Figure 8-4 ...

Page 94

... Enables timer overflow interrupts Controls the active edge polarity of the TCAP signal Controls the active level of the TCMP output $0012 Bit ICIE OCIE TOIE Unaffected Figure 8-5. Timer Control Register (TCR) Capture/Compare Timer Figure 8-5 performs these Bit IEDG OLVL MC68HC705C8A — Rev. 3 MOTOROLA ...

Page 95

... TCMP pin when a successful output compare occurs. Reset clears the OLVL bit. Bits 4–2 — Not used; these bits always read 0 MC68HC705C8A — Rev. 3 MOTOROLA 1 = Input capture interrupts enabled 0 = Input capture interrupts disabled 1 = Output compare interrupts enabled 0 = Output compare interrupts disabled ...

Page 96

... OLVL bit to the TCMP pin A timer rollover from $FFFF to $0000 $0013 Bit ICF OCF TOF Unimplemented U = Unaffected Figure 8-6. Timer Status Register (TSR Input capture input capture 1 = Output compare output compare Capture/Compare Timer Bit MC68HC705C8A — Rev. 3 MOTOROLA ...

Page 97

... Writing to the timer registers has no effect. Register Name and Address: Timer Register High — $0018 Read: Write: Reset: Register Name and Address: Timer Register Low — $0019 Read: Write: Reset: MC68HC705C8A — Rev. 3 MOTOROLA 1 = Timer overflow timer overflow Bit Bit 15 Bit 14 Bit 13 Reset initializes TRH to $FF ...

Page 98

... The buffer value remains fixed even if the high byte is read INTERNAL DATA BUS LATCH 15 $0018 TIMER REGISTER HIGH READ TRH Figure 8-8. Timer Register Reads Capture/Compare Timer 7 0 LOW BYTE BUFFER TIMER REGISTER LOW Figure 8-9 MC68HC705C8A — Rev. 3 MOTOROLA $0019 ...

Page 99

... Figure NOTE: To prevent interrupts from occurring between readings of ATRH and ATRL, set the interrupt mask (I bit) in the condition code register before reading ATRH, and clear the mask after reading ATRL. MC68HC705C8A — Rev. 3 MOTOROLA Bit Bit 15 Bit 14 Bit 13 ...

Page 100

... Bit 15 Bit 14 Bit 13 Bit 12 Unaffected by reset Bit 7 Bit 6 Bit 5 Bit 4 Unaffected by reset = Unimplemented Figure 8-11. Input Capture Registers (ICRH and ICRL) Capture/Compare Timer Figure 8-11. Reading ICRH before Bit 11 Bit 10 Bit 9 Bit 3 Bit 2 Bit 1 MC68HC705C8A — Rev. 3 MOTOROLA Bit 0 Bit 8 Bit 0 ...

Page 101

... Write to OCRH. Compares are now inhibited until OCRL is written. 3. Clear bit OCF by reading the timer status register (TSR). 4. Enable the output compare function by writing to OCRL. 5. Enable interrupts by clearing the I bit in the condition code register. MC68HC705C8A — Rev. 3 MOTOROLA Bit Bit 15 Bit 14 ...

Page 102

... Capture/Compare Timer Technical Data 102 Capture/Compare Timer MC68HC705C8A — Rev. 3 MOTOROLA ...

Page 103

... Introduction This section describes erasable, programmable read-only memory/one-time programmable read-only memory (EPROM/OTPROM (PROM)) programming. MC68HC705C8A — Rev. 3 MOTOROLA Section 9. EPROM/OTPROM (PROM) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 EPROM/OTPROM (PROM) Programming . . . . . . . . . . . . . . . 104 Program Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Preprogramming Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 PROM Programming Routines . . . . . . . . . . . . . . . . . . . . . . . . 111 Program and Verify PROM 111 Verify PROM Contents ...

Page 104

... EPROM/OTPROM (PROM) 9.3 EPROM/OTPROM (PROM) Programming The internal PROM can be programmed efficiently using the Motorola MC68HC05PGMR-2 programmer board, which can be purchased from a Motorola-authorized distributor. The user can program the microcontroller unit (MCU) using this printed circuit board (PCB) in conjunction with an EPROM device already programmed with user code. ...

Page 105

... MC68HC705C8A — Rev. 3 MOTOROLA START AT BEGINNING WRITE PROM DATA YES NTRYS = NTRYS + 1 NO Figure 9-1. EPROM/OTPROM Programming Flowchart EPROM/OTPROM (PROM) EPROM/OTPROM (PROM) EPROM/OTPROM (PROM) Programming START APPLY V PP NTRYS = 0 OF MEMORY LAT = 1 PGM = 1 WAIT 1 ms PGM = 0 LAT = 0 WRITE ADDITIONAL BYTE NO NTRYS = 2 ...

Page 106

... PB1 13 D1 PB1 PC1 13 (D2) PB2 14 D2 PB2 PC2 15 15 (D3) PB3 D3 PB3 PC3 16 (D4) PB4 16 D4 PB4 PC4 (D5 PB5 D5 PB5 18 (D6) PB6 18 D6 PB6 PB7 19 19 (D7) D7 PB7 PC7 MC68HC705C8A — Rev. 3 MOTOROLA A C1 100 (A8) 27 (A9) 26 (A10) 25 (A11) 24 (A12 ...

Page 107

... Y1 C4 2.0 MHz R10* 470 VERF DS2* (VERF) M (PROG) N PROG DS1* (A5) (A4) (A3) R11* (A2) 470 (A1) (A0 Figure 9-2. PROM Programming Circuit (Continued) MC68HC705C8A — Rev. 3 MOTOROLA R13 PA5 8 PA4 9 PA3 10 PA2 11 PA1 U3 12 PA0 44-LEAD PLCC (D0) 13 SOCKET PB0 (D1) 14 PB1 (D2) ...

Page 108

... Execute program in RAM Dump PROM contents (binary upload) Table 9-2. Table 9-2. PROM Programming Routines Routine EPROM/OTPROM (PROM Off Off Off Off Off Off On Off On Off On Off Off Off On Off Off Off Off Off On Off On On Off MC68HC705C8A — Rev. 3 MOTOROLA ...

Page 109

... Address: Read: Write: Reset: LAT — Latch Enable Bit This bit is both readable and writable. PGM — Program Bit If LAT is cleared, PGM cannot be set. Bits 1 and 3 7 — Not used; always read 0 MC68HC705C8A — Rev. 3 MOTOROLA $001C Bit Figure 9-3. Program Register (PROG) ...

Page 110

... MC68HC705C8S or MC68HC705C8P in socket U2 (40-pin dual in-line package (DIP)) or – MC68HC705C8FN in socket U3 (44-pin plastic leaded chip carrier (PLCC)) with the device notch at the upper right corner of the socket. (P1, slot EPROM/OTPROM (PROM (switch 1) is active on the board. DD MC68HC705C8A — Rev. 3 MOTOROLA ...

Page 111

... S6 to the positions necessary to select the next routine, and begin the routine by setting switch 2 to the OUT position other routine performed, remove V the programming socket. MC68HC705C8A — Rev. 3 MOTOROLA power source. PP proper routine). The red light-emitting diode (LED) is illuminated, showing that the programming part of the routine is running ...

Page 112

... When the green LED is illuminated, verification is completed successfully and the routine is finished. from the board and remove the MCU from the programming DD is necessary. Once this bit is PP EPROM/OTPROM (PROM MC68HC705C8A — Rev. 3 MOTOROLA ...

Page 113

... Set switches S3, S4, and S5 in the ON position. 5. Set switch 2 in the OUT position (routine is activated). 6. Set switch 2 in the RESET position when the routine is completed. MC68HC705C8A — Rev. 3 MOTOROLA power to the programming board. PP Execution time for this routine is about one second. ...

Page 114

... RESET position resets the MCU with the RAM data intact. Any other routine can be entered, including the one to execute the program in RAM, simply by setting switches S3–S6 as necessary to select the desired routine, then setting switch 2 in the OUT position. Technical Data 114 EPROM/OTPROM (PROM MC68HC705C8A — Rev. 3 MOTOROLA ...

Page 115

... Set switch 1 in the ON position (restores V 2. Connect V 3. Set switches S3 and S6 in the OFF position. 4. Set switches S4 and S5 in the ON position. 5. Set switch 2 in the OUT position (routine is activated). 6. Once PROM dumping is complete, set switch 2 in the RESET MC68HC705C8A — Rev. 3 MOTOROLA ...

Page 116

... Maps 96 bytes of RAM into page one starting at address $0100. This bit can be read or written at any time, allowing memory configuration to be changed during program execution Provides 96 bytes of PROM at location $0100. EPROM/OTPROM (PROM) is used to select the IRQ Bit 0 * SEC IRQ Unaffected MC68HC705C8A — Rev. 3 MOTOROLA ...

Page 117

... Erased: PBPU7–PBPU0/COPC — Port B Pullup Enable Bits 7–0 These EPROM bits enable the port B pullup devices. MC68HC705C8A — Rev. 3 MOTOROLA 1 = Security enabled 0 = Security off; bootloader able to be enabled 1 = IRQ pin is both negative edge- and level-sensitive IRQ pin is negative edge-sensitive only. ...

Page 118

... Technical Data 118 5.3.3 Programmable and 5.3.3 Programmable and Non-Programmable COP Watchdog $1FF1 Bit Unaffected by reset Unimplemented Figure 9-6. Mask Option Register 2 (MOR2 Non-programmable COP watchdog enabled 0 = Non-programmable COP watchdog disabled EPROM/OTPROM (PROM) Resets. Figure 9 EPROM MC68HC705C8A — Rev. 3 MOTOROLA Bit 0 NCOPE 0 ...

Page 119

... EPROM device should be positioned about one inch from the UV source. OTPROM devices are shipped in an erased state. Once programmed, they cannot be erased. Electrical erasing procedures cannot be performed on either EPROM or OTPROM devices. MC68HC705C8A — Rev. 3 MOTOROLA EPROM/OTPROM (PROM) EPROM/OTPROM (PROM) EPROM Erasing ...

Page 120

... EPROM/OTPROM (PROM) Technical Data 120 EPROM/OTPROM (PROM) MC68HC705C8A — Rev. 3 MOTOROLA ...

Page 121

... Introduction The serial communications interface (SCI) module allows high-speed asynchronous communication with peripheral devices and other microcontroller units (MCUs). MC68HC705C8A — Rev. 3 MOTOROLA Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 SCI Data Format 122 SCI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 SCI I/O Registers ...

Page 122

... Interrupt-driven operation capability with five interrupt flags: – Transmitter data register empty – Transmission complete – Receiver data register full – Receiver overrun – Idle receiver input Receiver framing error detection 1/16 bit-time noise detection Figure 10-1. Serial Communications Interface (SCI) MC68HC705C8A — Rev. 3 MOTOROLA ...

Page 123

... This subsection describes the operation of the SCI transmitter and receiver. 10.5.1 Transmitter Figure 10-2 summary of the SCI transmitter input/output (I/O) registers. • • MC68HC705C8A — Rev. 3 MOTOROLA 8-BIT DATA FORMAT (BIT M IN SCCR1 CLEAR) BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 ...

Page 124

... SCI RECEIVE REQUESTS SCI INTERRUPT REQUEST Technical Data 124 SCDR ($0011) TRANSMIT SHIFT REGISTER TRANSMITTER CONTROL LOGIC SCSR ($0010) TDRE TIE TC TCIE SCCR2 ($000F) Figure 10-2. SCI Transmitter Serial Communications Interface (SCI) PIN BUFFER PD1/ AND CONTROL TDO MC68HC705C8A — Rev. 3 MOTOROLA ...

Page 125

... SCI Control Register 2 $000F (SCCR2) See page 131. SCI Status Register $0010 (SCSR) See page 133. SCI Data Register $0011 (SCDR) See page 129. Figure 10-3. SCI Transmitter I/O Register Summary MC68HC705C8A — Rev. 3 MOTOROLA Bit Read: SCP1 Write: Reset Read ...

Page 126

... SCDR are empty and that no break or idle character has been generated source of SCI interrupt requests. The transmission complete interrupt enable bit (TCIE) in SCCR2 is the local mask for TC interrupts. Serial Communications Interface (SCI) MC68HC705C8A — Rev. 3 MOTOROLA ...

Page 127

... CLOCK PD0/ PIN BUFFER RDI AND CONTROL M SCCR1 ($000E) SCI TRANSMIT REQUESTS SCI INTERRUPT REQUEST MC68HC705C8A — Rev. 3 MOTOROLA shows the structure of the SCI receiver. Refer to for a summary of the SCI receiver I/O registers. 16 DATA RECOVERY DISABLE DRIVER RE SCSR ($0010) RDRF RIE ...

Page 128

... Any conflict between noise detection samples sets the noise flag (NF) in the SCSR. The NF bit is set at the same time that the RDRF bit is set. Serial Communications Interface (SCI) MC68HC705C8A — Rev. 3 MOTOROLA ...

Page 129

... Read: Write: Reset: MC68HC705C8A — Rev. 3 MOTOROLA Framing Errors — If the data recovery logic does not detect a logic 1 where the stop bit should incoming character, it sets the framing error (FE) bit in the SCSR. The FE bit is set at the same time that the RDRF bit is set. ...

Page 130

... Stores ninth SCI data bit received and ninth SCI data bit transmitted Controls SCI character length Controls SCI wakeup method $000E Bit Unimplemented Figure 10-6. SCI Control Register 1 (SCCR1 9-bit SCI characters 0 = 8-bit SCI characters Serial Communications Interface (SCI) Figure 10-6 has these Bit 0 WAKE Unaffected MC68HC705C8A — Rev. 3 MOTOROLA ...

Page 131

... TIE — Transmit Interrupt Enable Bit This read/write bit enables SCI interrupt requests when the TDRE bit becomes set. Reset clears the TIE bit. MC68HC705C8A — Rev. 3 MOTOROLA 1 = Address mark wakeup 0 = Idle line wakeup Enables the SCI receiver and SCI receiver interrupts ...

Page 132

... Technical Data 132 interrupt requests enabled interrupt requests disabled 1 = RDRF interrupt requests enabled 0 = RDRF interrupt requests disabled 1 = IDLE interrupt requests enabled 0 = IDLE interrupt requests disabled 1 = Transmission enabled 0 = Transmission disabled 1 = Receiver enabled 0 = Receiver disabled Serial Communications Interface (SCI) MC68HC705C8A — Rev. 3 MOTOROLA ...

Page 133

... Address: Read: Write: Reset: MC68HC705C8A — Rev. 3 MOTOROLA 1 = Standby state 0 = Normal operation 1 = Break codes being transmitted break codes being transmitted Transfer of SCDR data to transmit shift register complete Transmission complete Transfer of receive shift register data to SCDR complete Receiver input idle ...

Page 134

... SCDR data transferred to transmit shift register 0 = SCDR data not transferred to transmit shift register transmission in progress 0 = Transmission in progress 1 = Received data available in SCDR 0 = Received data not available in SCDR 1 = Receiver input idle 0 = Receiver input not idle Serial Communications Interface (SCI) MC68HC705C8A — Rev. 3 MOTOROLA ...

Page 135

... OR bit is set and the FE bit is not set. Clear the FE bit by reading the SCSR and then reading the SCDR. Reset clears the FE bit. MC68HC705C8A — Rev. 3 MOTOROLA 1 = Receiver shift register full and RDRF = receiver overrun 1 = Noise detected in SCDR noise detected in SCDR ...

Page 136

... Resets clear both SCP1 and SCP0. Table 10-1. Baud Rate Generator Clock Prescaling SCP[1:0] Baud Rate Generator Clock Serial Communications Interface (SCI) selects the baud rate for Bit 0 SCR2 SCR1 SCR0 Unaffected Internal clock 1 Internal clock 3 Internal clock 4 Internal clock 13 MC68HC705C8A — Rev. 3 MOTOROLA ...

Page 137

... SCR2–SCR0 — SCI Baud Rate Select Bits Table 10-3 frequencies of 2 MHz, 4 MHz, and 4.194304 MHz. MC68HC705C8A — Rev. 3 MOTOROLA These read/write bits select the SCI baud rate, as shown in Table 10-2. Reset has no effect on the SCR2–SCR0 bits. Table 10-2. Baud Rate Selection ...

Page 138

... Kbaud 4808 baud 5041 baud 2404 baud 2521 baud 1202 baud 1260 baud 601.0 baud 630.2 baud 300.5 baud 315.1 baud 150.2 baud 157.5 baud 75.12 baud 78.77 baud MC68HC705C8A — Rev. 3 MOTOROLA ...

Page 139

... Introduction The serial peripheral interface (SPI) module allows full-duplex, synchronous, serial communication with peripheral devices. MC68HC705C8A — Rev. 3 MOTOROLA Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Pin Functions in Master Mode . . . . . . . . . . . . . . . . . . . . . . 143 Pin Functions in Slave Mode . . . . . . . . . . . . . . . . . . . . . . .144 Multiple-SPI Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Serial Clock Polarity and Phase ...

Page 140

... Four programmable master mode frequencies (1.05 MHz maximum) 2.1-MHz maximum slave mode frequency Serial clock with programmable polarity and phase End of transmission interrupt flag Write collision error flag Bus contention error flag shows the structure of the SPI module. Serial Peripheral Interface (SPI) Figure 11 MC68HC705C8A — Rev. 3 MOTOROLA ...

Page 141

... INTERNAL CLOCK (XTAL 2) DIVIDER SELECT SPI CONTROL SPSR ($000B) SPI INTERRUPT MC68HC705C8A — Rev. 3 MOTOROLA SPI SHIFT REGISTER SPDR ($000C) SPI CLOCK (MASTER) MSTR SPE SPIE INTERNAL REQUEST DATA BUS Figure 11-1. SPI Block Diagram Serial Peripheral Interface (SPI) Serial Peripheral Interface (SPI) ...

Page 142

... Read: SPIE SPE Write: Reset Read: SPIF WCOL MODF Write: Reset Read: Bit 7 Bit 6 Bit 5 Write: Reset: = Unimplemented U = Unaffected Serial Peripheral Interface (SPI MSTR CPOL CPHA SPR1 Bit 4 Bit 3 BIt 2 Bit 1 Unaffected by reset MC68HC705C8A — Rev. 3 MOTOROLA Bit 0 SPR0 U Bit 0 ...

Page 143

... Setting the MSTR bit in the SPI control register (SPCR) configures the SPI for operation in master mode. The master-mode functions of the SPI pins are: • • • • MC68HC705C8A — Rev. 3 MOTOROLA shows how a master SPI exchanges data with a slave SPI. PD3/MOSI SPI SHIFT REGISTER PD2/MISO SPDR ($000C) PD4/SCK MASTER MCU Figure 11-3 ...

Page 144

... CPOL, CPHA, SPR1, and SPR0 bits set to the desired logic levels. If this procedure is followed after a reset and before the first access to the SPDR, the WCOL flag will not be set. Serial Peripheral Interface (SPI) MC68HC705C8A — Rev. 3 MOTOROLA ...

Page 145

... Before a transmission, one SPI is configured as master and the rest are configured as slaves. master SPI and three slave SPIs. Figure 11-5 three slave SPIs. MC68HC705C8A — Rev. 3 MOTOROLA ; MSTR = 1, CPOL = 1, CPHA = 1, ; SPR1 = SPR0 = 0 ; SPI control register ; MSTR = 0, SPE = 1, CPOL = 1, CPHA = 1, ; SPR1 = SPR0 = 0 ...

Page 146

... SLAVE MCU 2 SLAVE MCU 1 BIT 6 BIT 5 BIT 4 BIT 3 Figure 11-6. SPI Clock/Data Timing Serial Peripheral Interface (SPI) MASTER/SLAVE MCU 2 PD2/MISO PD3/MOSI PD4/SCK PD5/ I/O PORT 2 3 SLAVE MCU 0 Figure 11-6 shows how the CPOL BIT 2 BIT 1 LSB MC68HC705C8A — Rev. 3 MOTOROLA ...

Page 147

... MC68HC705C8A — Rev. 3 MOTOROLA Bus contention caused by multiple master SPIs (mode fault error) Writing to the SPDR during a transmission (write-collision error) Failing to read the SPDR before the next incoming byte sets the SPIF bit (overrun error) ...

Page 148

... SCK cycle. The error does not affect the transmission from the master SPI, but the byte that caused the error is lost. SPI data register (SPDR) SPI control register (SPCR) SPI status register (SPSR) Serial Peripheral Interface (SPI) MC68HC705C8A — Rev. 3 MOTOROLA ...

Page 149

... Address: Read: Write: Reset: SPIE — SPI Interrupt Enable Bit This read/write bit enables SPI interrupts. Reset clears the SPIE bit. MC68HC705C8A — Rev. 3 MOTOROLA Figure 11-7 $000C Bit Bit 7 Bit 6 Bit 5 Unaffected by reset Figure 11-7. SPI Data Register (SPDR) ...

Page 150

... First active edge on PD4/SCK latches data Table 11-1. The SPR1 and SPR0 bits of a slave SPI have Table 11-1. SPI Clock Rate Selection SPR[1: Serial Peripheral Interface (SPI) SPI Clock Rate Internal Clock 2 Internal Clock 4 Internal Clock 16 Internal Clock 32 MC68HC705C8A — Rev. 3 MOTOROLA ...

Page 151

... This clearable, read-only flag is set when software writes to the SPDR while a transmission is in progress. Clear the WCOL bit by reading the SPSR with WCOL set and then reading or writing the SPDR. Reset clears WCOL. MC68HC705C8A — Rev. 3 MOTOROLA Figure 11-9 SPI transmission complete Write collision Mode fault ...

Page 152

... SPIE bit is also set. Clear the MODF bit by reading the SPSR with MODF set and then writing to the SPCR. Reset clears MODF. Technical Data 152 1 = PD5/SS pulled low while MSTR bit set 0 = PD5/SS not pulled low while MSTR bit set Serial Peripheral Interface (SPI) MC68HC705C8A — Rev. 3 MOTOROLA ...

Page 153

... MC68HC705C8A — Rev. 3 MOTOROLA Section 12. Instruction Set Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Immediate 155 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Indexed, 8-Bit Offset 156 Indexed, 16-Bit Offset 156 Relative ...

Page 154

... The addressing modes provide eight different ways for the CPU to find the data required to execute an instruction. The eight addressing modes are: • • • • • • • • Technical Data 154 Inherent Immediate Direct Extended Indexed, no offset Indexed, 8-bit offset Indexed, 16-bit offset Relative Instruction Set MC68HC705C8A — Rev. 3 MOTOROLA ...

Page 155

... The first byte is the opcode; the second and third bytes are the high and low bytes of the operand address. When using the Motorola assembler, the programmer does not need to specify whether an instruction is direct or extended. The assembler automatically selects the shortest form of the instruction. ...

Page 156

... The first byte after the opcode is the high byte of the 16-bit offset; the second byte is the low byte of the offset. Indexed, 16-bit offset instructions are useful for selecting the kth element in an n-element table anywhere in memory. As with direct and extended addressing, the Motorola assembler determines the shortest form of indexed addressing. Technical Data 156 Instruction Set MC68HC705C8A — ...

Page 157

... When using the Motorola assembler, the programmer does not need to calculate the offset, because the assembler determines the proper offset and verifies that it is within the span of the branch. ...

Page 158

... Subtract memory byte and carry bit from accumulator Store accumulator in memory Store index register in memory Subtract memory byte from accumulator Instruction Set Mnemonic ADC ADD AND BIT CMP CPX EOR LDA LDX MUL ORA SBC STA STX SUB MC68HC705C8A — Rev. 3 MOTOROLA ...

Page 159

... These instructions read a memory location or a register, modify its contents, and write the modified value back to the memory location or to the register. NOTE: Do not use read-modify-write operations on write-only registers. MC68HC705C8A — Rev. 3 MOTOROLA Table 12-2. Read-Modify-Write Instructions Instruction Arithmetic shift left (same as LSL) Arithmetic shift right Bit clear ...

Page 160

... The span of branching is from –128 to +127 from the address of the next location after the branch instruction. The CPU also transfers the tested bit to the carry/borrow bit of the condition code register. Technical Data 160 Instruction Set MC68HC705C8A — Rev. 3 MOTOROLA ...

Page 161

... MC68HC705C8A — Rev. 3 MOTOROLA Table 12-3. Jump and Branch Instructions Instruction Branch if carry bit clear Branch if carry bit set Branch if equal Branch if half-carry bit clear Branch if half-carry bit set Branch if higher Branch if higher or same Branch if IRQ pin high Branch if IRQ pin low ...

Page 162

... CPU can also test and branch based on the state of any bit in any of the first 256 memory locations. Technical Data 162 Table 12-4. Bit Manipulation Instructions Instruction Bit clear Branch if bit clear Branch if bit set Bit set Instruction Set Mnemonic BCLR BRCLR BRSET BSET MC68HC705C8A — Rev. 3 MOTOROLA ...

Page 163

... Control Instructions These instructions act on CPU registers and control CPU operation during program execution. MC68HC705C8A — Rev. 3 MOTOROLA Table 12-5. Control Instructions Instruction Clear carry bit Clear interrupt mask No operation Reset stack pointer Return from interrupt Return from subroutine Set carry bit ...

Page 164

... IX2 IX1 IMM DIR EXT — IX2 IX1 DIR 38 5 INH INH 58 3 IX1 DIR 37 5 INH INH 57 3 IX1 REL DIR (b0 DIR (b1 DIR (b2 DIR (b3 DIR (b4 DIR (b5 DIR (b6 DIR (b7 REL REL REL REL REL REL MC68HC705C8A — Rev. 3 MOTOROLA ...

Page 165

... BRN rel Branch Never BRSET n opr rel Branch if Bit n Set BSET n opr Set Bit n BSR rel Branch to Subroutine CLC Clear Carry Bit CLI Clear Interrupt Mask MC68HC705C8A — Rev. 3 MOTOROLA Description PC (PC rel ? IRQ = 1 PC (PC rel ? IRQ = 0 (A) (M) PC (PC rel ? (PC rel ? — ...

Page 166

... IX1 DIR 33 5 INH INH 53 3 IX1 IMM DIR EXT IX2 IX1 DIR 3A 5 INH — INH 5A 3 IX1 IMM DIR EXT — IX2 IX1 DIR 3C 5 INH — INH 5C 3 IX1 DIR EXT IX2 IX1 MC68HC705C8A — Rev. 3 MOTOROLA ...

Page 167

... ORA opr Logical OR Accumulator with Memory ORA opr,X ORA opr,X ORA ,X ROL opr ROLA ROLX Rotate Byte Left through Carry Bit ROL opr,X ROL ,X MC68HC705C8A — Rev. 3 MOTOROLA Description PC (PC Push (PCL); SP (SP) – 1 Push (PCH); SP (SP) – Effective Address A (M) ...

Page 168

... INH 56 3 IX1 INH 9C 2 INH 80 9 INH IMM DIR EXT IX2 IX1 INH 99 2 INH DIR EXT — IX2 IX1 INH DIR EXT — IX2 IX1 IMM DIR EXT IX2 IX1 INH 83 0 INH 97 2 MC68HC705C8A — Rev. 3 MOTOROLA ...

Page 169

... Indexed, no offset addressing mode IX1 Indexed, 8-bit offset addressing mode IX2 Indexed, 16-bit offset addressing mode M Memory location N Negative flag n Any bit 12.6 Opcode Map See MC68HC705C8A — Rev. 3 MOTOROLA Description (M) – $00 A Table 12-7. Instruction Set Instruction Set Effect on CCR DIR INH   — ...

Page 170

Bit Manipulation Branch Read-Modify-Write DIR DIR REL DIR INH MSB LSB BRSET0 BSET0 BRA NEG NEGA 3 DIR 2 DIR 2 REL 2 DIR 1 INH ...

Page 171

... Serial Peripheral Interface (SPI) Timing . . . . . . . . . . 185 13.12 3.3-Volt Serial Peripheral Interface (SPI) Timing . . . . . . . . . . 187 13.2 Introduction This section contains electrical and timing specifications. MC68HC705C8A — Rev. 3 MOTOROLA Section 13. Electrical Specifications Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Operating Temperature Range 173 Thermal Characteristics ...

Page 172

... Connect unused inputs to the appropriate In Out (1) Symbol Rating and 13.7 5.0-Volt DC Electrical Characteristics Electrical Specifications within the range Out Value Unit V –0 –0 +0 –0 16.0 V – –65 to +150 STG and for guaranteed operating MC68HC705C8A — Rev. 3 MOTOROLA ...

Page 173

... Thermal resistance Plastic dual in-line package (DIP) Ceramic dual in-line package (cerdip) Plastic leaded chip carrier (PLCC) Quad flat pack (QFP) Plastic shrink DIP (SDIP) TEST POINT C (SEE TABLE) MC68HC705C8A — Rev. 3 MOTOROLA (1) Rating (2) MC68HC705C8ACB MC68HC705C8ACFB MC68HC705C8ACFS MC68HC705C8ACP MC68HC705C8ACFN MC68HC705C8ACFS Plastic dual in-line package (PDIP) ...

Page 174

... I/O < P I/O INT , the relationship between P I 273 273 Using this value of K, the values Electrical Specifications , in C can be obtained from and can be neglected. and T is approximately (at equilibrium) for a D and T can be obtained MC68HC705C8A — Rev. 3 MOTOROLA (1) (2) (3) ...

Page 175

... DD than all outputs OSC2 disabled. If SPI and SCI enabled, add 10% current draw. OSC2 capacitance linearly affects wait I 6. Stop I measured with OSC1 = V DD MC68HC705C8A — Rev. 3 MOTOROLA (1) Symbol Figure 13-3) 13- unless otherwise noted A ...

Page 176

... DD — — — — — — 0.3 — — 0.3 0 — 0 — 2.0 — — — 1.53 3.0 — 0.711 1.0 — 2.0 20 — — 10 — — 2.0 MHz). All inputs 0.2 V from rail DD – 0 MC68HC705C8A — Rev. 3 MOTOROLA Unit ...

Page 177

... MC68HC705C8A — Rev. 3 MOTOROLA 5.0 4.0 3.0 2.0 1.0 0.8 SEE NOTE 2 0 0.2 V – Notes 5.0 V, devices are specified and tested for (V DD 800 –0.8 mA 3.3 V, devices are specified and tested for (V DD 300 –0.2 mA. OH (a) V versus I for Ports A, B, PC6–PC0, and TCMP ...

Page 178

... V (VOLTS) OL Notes 5.0 V, devices are specified and tested for DD V 400 1.6 mA 3.3 V, devices are specified and tested for DD V 300 0.4 mA (c) V versus I for All Ports Except PC7 OL OL Electrical Specifications SEE NOTE 1 0.3 0.4 MC68HC705C8A — Rev. 3 MOTOROLA ...

Page 179

... MC68HC705C8A — Rev. 3 MOTOROLA 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0.0 0.5 1.0 INTERNAL FREQUENCY 1 t (a) Wait Mode 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0.0 0.5 1.0 INTERNAL FREQUENCY 1 t (b) Run Mode Figure 13-3 ...

Page 180

... MHz INTERNAL CLOCK FREQUENCY (XTAL (b) Maximum Current Drain versus Frequency @ 5 V Figure 13-4. Total Current Drain versus Frequency Electrical Specifications (20 A) STOP MHz 750 kHz STOP I ( MHz 1.5 MHz 2) 10% MC68HC705C8A — Rev. 3 MOTOROLA ...

Page 181

... TLTL vice routine plus CYC 4. The minimum period should not be less than the number of cycle times it takes to execute the interrupt service routine ILIL plus CYC MC68HC705C8A — Rev. 3 MOTOROLA (1) Symbol f OSC CYC t Figure 13-7) ...

Page 182

... Figure 13-5. Timer Relationships Electrical Specifications Min Max Unit — 2.0 MHz dc 2.0 — 1.0 MHz dc 1.0 1000 — ns — 100 ms — 100 — CYC t 4.0 — CYC 250 — ns (3) — t CYC 250 — ns (4) t — CYC 200 — MC68HC705C8A — Rev. 3 MOTOROLA ...

Page 183

... Notes: 1. Represents the internal gating of the OSC1 pin 2. IRQ pin edge-sensitive option 3. IRQ pin level and edge-sensitive option 4. RESET vector address shown for timing example Figure 13-6. Stop Recovery Timing Diagram MC68HC705C8A — Rev. 3 MOTOROLA t 4064 t ILCH CYC 1FFE 1FFE Electrical Specifications Electrical Specifications 3 ...

Page 184

VDDR V V THRESHOLD (1-2 V TYPICAL OSC1 t OXOV t CYC INTERNAL PROCESSOR CLOCK INTERNAL ADDRESS 1FFE 1FFF NEW PC ** BUS INTERNAL OP NEW NEW DATA PCH CODE PCL *** BUS RESET * OSC1 ...

Page 185

... Data hold time (inputs) Master 7 Slave (4) Access time 8 Slave (5) Disable time 9 Slave Data valid time Master (before capture edge) 10 Slave (after enable edge) MC68HC705C8A — Rev. 3 MOTOROLA (2) Characteristic (6) Electrical Specifications Electrical Specifications 5.0-Volt Serial Peripheral Interface (SPI) Timing Symbol Min Max f dc 0.5 OP( 2.1 ...

Page 186

... With 200 pF on all SPI pins 200 70 20 200 Technical Data 186 (2) Symbol t HO(M) t HO(S) t R(M) t R(S) t F(M) t F(S) and Figure 13-9. Electrical Specifications Min Max Unit t 0.25 — CYC(M) 0 — ns — 100 ns — 2.0 s — 100 ns — 2.0 s MC68HC705C8A — Rev. 3 MOTOROLA ...

Page 187

... Data hold time (inputs) Master 7 Slave (4) Access time 8 Slave (5) Disable time 9 Slave Data valid time Master (before capture edge) 10 Slave (after enable edge) MC68HC705C8A — Rev. 3 MOTOROLA (2) Characteristic (6) Electrical Specifications Electrical Specifications 3.3-Volt Serial Peripheral Interface (SPI) Timing Symbol Min Max f 0.5 OP( 2.1 OP( ...

Page 188

... With 200 pF on all SPI pins 200 70 20 200 Technical Data 188 (2) Symbol t HO(M) t HO(S) t R(M) t R(S) t F(M) t F(S) and Figure 13-9. Electrical Specifications Min Max Unit t 0.25 — CYC(M) 0 — ns — 200 ns — 2.0 s — 200 ns — 2.0 s MC68HC705C8A — Rev. 3 MOTOROLA ...

Page 189

... SS pin of master held high. INPUT SCK (CPOL = 0) OUTPUT SCK (CPOL = 1) OUTPUT MISO INPUT 10 MOSI OUTPUT 13 Note: This last clock edge is generated internally, but is not seen at the SCK pin. MC68HC705C8A — Rev. 3 MOTOROLA MSB IN BITS 6–1 11 MASTER MSB OUT BITS 6–1 a) SPI Master Timing (CPHA = ...

Page 190

... MSB OUT BITS 6– BITS 6–1 a) SPI Slave Timing (CPHA = SLAVE MSB OUT BITS 6– MSB IN BITS 6–1 b) SPI Slave Timing (CPHA = 1) Figure 13-9. SPI Slave Timing Electrical Specifications SLAVE LSB OUT NOTE 11 LSB SLAVE LSB OUT 11 LSB IN MC68HC705C8A — Rev. 3 MOTOROLA ...

Page 191

... MC68HC705C8A — Rev. 3 MOTOROLA Section 14. Mechanical Specifications Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 40-Pin Plastic Dual In-Line Package (PDIP .192 40-Pin Ceramic Dual In-Line Package (Cerdip 193 44-Lead Plastic-Leaded Chip Carrier (PLCC 194 44-Lead Ceramic-Leaded Chip Carrier (CLCC 195 44-Pin Quad Flat Pack (QFP) ...

Page 192

... TOLERANCE OF LEADS (D), SHALL BEWITHIN 0.25 (0.010) AT MAXIMUM MATERIAL CONDITIONS, IN RELATION TO SEATING PLANE AND EACH OTHER. 2.DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3.DIMENSION B DOES NOT INCLUDE MOLD FLASH. MC68HC705C8A — Rev. 3 MOTOROLA MAX 2.065 0.560 0.200 0.022 0.060 0.085 0.015 ...

Page 193

... Ceramic Dual In-Line Package (Cerdip SEATING PLANE G F Figure 14-2. MC68HC705C8AS Package Dimensions (Case #734A) MC68HC705C8A — Rev. 3 MOTOROLA 40-Pin Ceramic Dual In-Line Package (Cerdip DATUM PLANE 0.25(0.010 Mechanical Specifications Mechanical Specifications INCHES MILLIMETERS DIM MIN MAX MIN MAX A 2 ...

Page 194

... BSC 0.032 0.66 0.81 0.51 0.64 0.656 16.51 16.66 0.656 16.51 16.66 0.048 1.07 1.21 0.048 1.07 1.21 0.056 1.07 1.42 0.020 0. 0.630 15.50 16.00 1.02 MC68HC705C8A — Rev. 3 MOTOROLA ...

Page 195

... Ceramic-Leaded Chip Carrier (CLCC) - 0.25 (0.010 DETAIL S Figure 14-4. MC68HC705C8AFS Package Dimensions (Case #777B) MC68HC705C8A — Rev. 3 MOTOROLA Y BRK DETAIL D 0.20 (0.008 0.18 (0.007 0.18 (0.007 0.10 (0.004) J -T- SEATING PLANE DETAIL 0.18 (0.007 0.18 (0.007 0.18 (0.007 0.18 (0.007) ...

Page 196

... PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. INCHES MAX 0.398 0.398 0.096 0.018 0.083 0.016 --- 0.010 0.009 0.037 5 10 0.007 0 7 0.012 0.530 --- 0 --- 0.530 --- MC68HC705C8A — Rev. 3 MOTOROLA S ...

Page 197

... Shrink Dual In-Line Package (SDIP) - -T- SEATING PLANE 0.25 (0.010 Figure 14-6. MC68HC705C8AB Package Dimensions (Case #858) MC68HC705C8A — Rev. 3 MOTOROLA 22 - 0.25 (0.010 Mechanical Specifications Mechanical Specifications 42-Pin Shrink Dual In-Line Package (SDIP) NOTES: 1. DIMENSIONS AND TOLERANCING PER ANSI Y14.5M, 1982. ...

Page 198

... Mechanical Specifications Technical Data 198 Mechanical Specifications MC68HC705C8A — Rev. 3 MOTOROLA ...

Page 199

... Section 15. Ordering Information Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 MCU Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 lists the MC order numbers. Temperature Range – +85 C – +85 C – +85 C – +85 C – +85 C – +85 C Ordering Information Order Number (1) (2) MC68HC705C8AC P (3) MC68HC705C8ACFN (4) MC68HC705C8ACFS (5) MC68HC705C8ACS (6) MC68HC705C8ACFB (7) MC68HC705C8ACB Technical Data 199 ...

Page 200

... Ordering Information Technical Data 200 Ordering Information MC68HC705C8A — Rev. 3 MOTOROLA ...

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