AT32UC3A4256 Atmel Corporation, AT32UC3A4256 Datasheet - Page 322

• Manufacturer Part Number: AT32UC3A4256
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A4256

• Flash (kbytes): 256 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

19.6
19.7
19.8
32072G–11/2011
Arbitration for HSB Master Interface
Memory Peripherals
Handshaking Interface
Each DMACA channel has two request lines that request ownership of a particular master bus
interface: channel source and channel destination request lines.
Source and destination arbitrate separately for the bus. Once a source/destination state
machine gains ownership of the master bus interface and the master bus interface has owner-
ship of the HSB bus, then HSB transfers can proceed between the peripheral and the DMACA.
An arbitration scheme decides which of the request lines (2 * DMAH_NUM_CHANNELS) is
granted the particular master bus interface. Each channel has a programmable priority. A
request for the master bus interface can be made at any time, but is granted only after the cur-
rent HSB transfer (burst or single) has completed. Therefore, if the master interface is
transferring data for a lower priority channel and a higher priority channel requests service, then
the master interface will complete the current burst for the lower priority channel before switch-
ing to transfer data for the higher priority channel.
If only one request line is active at the highest priority level, then the request with the highest pri-
ority wins ownership of the HSB master bus interface; it is not necessary for the priority levels to
be unique.
If more than one request is active at the highest requesting priority, then these competing
requests proceed to a second tier of arbitration:
If equal priority requests occur, then the lower-numbered channel is granted.
In other words, if a peripheral request attached to Channel 7 and a peripheral request attached
to Channel 8 have the same priority, then the peripheral attached to Channel 7 is granted first.
Figure 19-3 on page 318
eral. There is no handshaking interface with the DMACA, and therefore the memory peripheral
can never be a flow controller. Once the channel is enabled, the transfer proceeds immediately
without waiting for a transaction request. The alternative to not having a transaction-level hand-
shaking interface is to allow the DMACA to attempt System Bus transfers to the peripheral once
the channel is enabled. If the peripheral slave cannot accept these System Bus transfers, it
inserts wait states onto the bus until it is ready; it is not recommended that more than 16 wait
states be inserted onto the bus. By using the handshaking interface, the peripheral can signal to
the DMACA that it is ready to transmit/receive data, and then the DMACA can access the
peripheral without the peripheral inserting wait states onto the bus.
Handshaking interfaces are used at the transaction level to control the flow of single or burst
transactions. The operation of the handshaking interface is different and depends on whether
the peripheral or the DMACA is the flow controller.
The peripheral uses the handshaking interface to indicate to the DMACA that it is ready to trans-
fer/accept data over the System Bus. A non-memory peripheral can request a DMA transfer
through the DMACA using one of two handshaking interfaces:
• Hardware handshaking
• Software handshaking
shows the DMA transfer hierarchy of the DMACA for a memory periph-
322