AT32UC3A4256 Atmel Corporation, AT32UC3A4256 Datasheet - Page 699

• Manufacturer Part Number: AT32UC3A4256
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A4256

• Flash (kbytes): 256 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

26.8.2.14
Register Name:
Access Type:
Offset:
Reset Value:
• STALLRQ: STALL Request
• RSTDT: Reset Data Toggle
• NYETDIS: NYET token disable
• EPDISHDMA: Endpoint Interrupts Disable HDMA Request Enable
32072G–11/2011
PACKETE
SHORT
31
23
15
7
-
-
-
This bit is set when the STALLRQS bit is written to one. This will request to send a STALL handshake to the host.
This bit is cleared when a new SETUP packet is received or when the STALLRQC bit is written to zero.
This bit is set when the RSTDTS bit is written to one. This will clear the data toggle sequence, i.e., set to Data0 the data toggle
sequence of the next sent (IN endpoints) or received (OUT endpoints) packet.
This bit is cleared instantaneously.
The user does not have to wait for this bit to be cleared.
This bit is set when the NYETDISS bit is written to one. This will send a ACK handshake instead of a NYET handshake in high-
speed mode.
This bit is cleared when the NYETDISC bit is written to one.This will let the USBB handling the high-speed handshake following
the usb 2.0 standard.
This bit is set when the EPDISHDMAS is written to one. This will pause the on-going DMA channel n transfer on any Endpoint n
interrupt (EPnINT), whatever the state of the Endpoint n Interrupt Enable bit (EPnINTE).
The user then has to acknowledge or to disable the interrupt source (e.g. RXOUTI) or to clear the EPDISHDMA bit (by writing a
one to the EPDISHDMAC bit) in order to complete the DMA transfer.
In ping-pong mode, if the interrupt is associated to a new system-bank packet (e.g. Bank1) and the current DMA transfer is
running on the previous packet (Bank0), then the previous-packet DMA transfer completes normally, but the new-packet DMA
transfer will not start (not requested).
If the interrupt is not associated to a new system-bank packet (NAKINI, NAKOUTI, etc.), then the request cancellation may
occur at any time and may immediately pause the current DMA transfer.
This may be used for example to identify erroneous packets, to prevent them from being transferred into a buffer, to complete a
DMA transfer by software after reception of a short packet, etc.
Endpoint n Control Register
STALLEDE/
CRCERRE
FIFOCON
30
22
14
6
-
-
UECONn, n in [0..7]
Read-Only
0x01C0 + (n * 0x04)
0x00000000
OVERFE
KILLBK
29
21
13
5
-
-
NBUSYBKE
HBISOFLUSHE
NAKINE/
28
20
12
4
-
-
HBISOINERRE
NAKOUTE/
STALLRQ
27
19
11
3
-
-
ERRORTRANSE
UNDERFE
RXSTPE/
RSTDT
26
18
10
2
-
NYETDIS
RXOUTE
DATAXE
25
17
9
1
-
EPDISHDMA
MDATAE
TXINE
24
16
8
0
-
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