AT32UC3A4256 Atmel Corporation, AT32UC3A4256 Datasheet - Page 556

• Manufacturer Part Number: AT32UC3A4256
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A4256

• Flash (kbytes): 256 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

25.6.3.3
32072G–11/2011
Asynchronous Receiver
Figure 25-10. Bit Resynchronization
If the USART is configured in an asynchronous operating mode (MR.SYNC = 0), the receiver will
oversample the RXD input line by either 8 or 16 times the baud rate clock, as selected by the
Oversampling Mode bit (MR.OVER). If the line is zero for half a bit period (four or eight consecu-
tive samples, respectively), a start bit will be assumed, and the following 8th or 16th sample will
determine the logical value on the line, in effect resulting in bit values being determined at the
middle of the bit period.
The number of data bits, endianess, parity mode, and stop bits are selected by the same bits
and fields as for the transmitter (MR.CHRL, MODE9, MSBF, PAR, and NBSTOP). The synchro-
nization mechanism will only consider one stop bit, regardless of the used protocol, and when
the first stop bit has been sampled, the receiver will automatically begin looking for a new start
bit, enabling resynchronization even if there is a protocol miss-match.
25-12
Figure 25-11. Asynchronous Start Bit Detection
Clock (x16)
Baud Rate
Sampling
Sampling
Sampling
Oversampling
illustrate start bit detection and character reception in asynchronous mode.
Clock
RXD
RXD
Sampling
16x Clock
point
RXD
1
1
2
2
3
3
4
4
Synchro.
5
5
Error
6
6
7
Detection
7
Rejection
Start
Start
8
0
Synchro.
1
1
Jump
2
2
3
3
4
4
Expected edge
Tolerance
5
6
7
8
Jump
9 10 11 12 13 14 15 16
Sync
Figure 25-11
Synchro.
Error
and
Sampling
Figure
D0
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