AT32UC3A4256 Atmel Corporation, AT32UC3A4256 Datasheet - Page 651

• Manufacturer Part Number: AT32UC3A4256
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A4256

• Flash (kbytes): 256 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

26.7.3.12
26.7.3.13
32072G–11/2011
TXOUTI
FIFOCON
CRC error
Interrupts
•Global interrupts
TXOUTI
FIFOCON
SW
Figure 26-27. Example of an OUT Pipe with two Data Banks and no Bank Switching Delay
Figure 26-28. Example of an OUT Pipe with two Data Banks and a Bank Switching Delay
This error exists only for isochronous IN pipes. It set the CRC Error Interrupt (CRCERRI) bit,
what triggers a PnINT interrupt if then the CRC Error Interrupt Enable (CRCERRE) bit in
UPCONn is one.
A CRC error can occur during IN stage if the USBB detects a corrupted received packet. The IN
packet is stored in the bank as if no CRC error had occurred (RXINI is set).
See the structure of the USB host interrupt system on
There are two kinds of host interrupts: processing, i.e. their generation is part of the normal pro-
cessing, and exception, i.e. errors (not related to CPU exceptions).
The processing host global interrupts are:
write data to CPU
• The Device Connection Interrupt (DCONNI)
• The Device Disconnection Interrupt (DDISCI)
SW
BANK 0
write data to CPU
BANK 0
SW
OUT
SW
SW
OUT
write data to CPU
SW
BANK 1
(bank 0)
(bank 0)
DATA
DATA
write data to CPU
BANK 1
ACK
HW
SW
ACK
HW
Figure 26-6 on page
SW
SW
OUT
OUT
write data to CPU
BANK0
SW
(bank 1)
DATA
write data to CPU
(bank 1)
DATA
BANK0
625.
ACK
ACK
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