ATtiny2313 Atmel Corporation, ATtiny2313 Datasheet - Page 16

• Manufacturer Part Number: ATtiny2313
• Manufacturer: Atmel Corporation

Specifications of ATtiny2313

• Flash (kbytes): 2 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 20 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 4
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 18
• Ext Interrupts: 18
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.12
• Eeprom (bytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

EEPROM Data
Memory
EEPROM Read/Write
Access
The EEPROM Address
Register
16
ATtiny2313
Figure 10. On-chip Data SRAM Access Cycles
The ATtiny2313 contains 128 bytes of data EEPROM memory. It is organized as a separate
data space, in which single bytes can be read and written. The EEPROM has an endurance of at
least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described
in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and
the EEPROM Control Register. For a detailed description of Serial data downloading to the
EEPROM, see
The EEPROM Access Registers are accessible in the I/O space.
The write access time for the EEPROM is given in
the user software detect when the next byte can be written. If the user code contains instructions
that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, V
is likely to rise or fall slowly on power-up/down. This causes the device for some period of time to
run at a voltage lower than specified as minimum for the clock frequency used.
EEPROM Corruption” on page 20.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.
Refer to the description of the EEPROM Control Register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is
executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next
instruction is executed.
• Bit 7 – Res: Reserved Bit
This bit is reserved in the ATtiny2313 and will always read as zero.
Bit
Read/Write
Initial Value
Address
clk
page
Data
Data
R
7
–
0
WR
CPU
RD
172.
EEAR6
R/W
X
6
Compute Address
EEAR5
R/W
X
5
T1
Memory Access Instruction
for details on how to avoid problems in these situations.
EEAR4
R/W
X
4
EEAR3
R/W
Address valid
3
X
Table
T2
EEAR2
R/W
2
X
1. A self-timing function, however, lets
EEAR1
R/W
Next Instruction
1
X
T3
EEAR0
R/W
0
X
See “Preventing
EEAR
2543L–AVR–08/10
CC