ATtiny861 Automotive Atmel Corporation, ATtiny861 Automotive Datasheet - Page 149
ATtiny861 Automotive
Manufacturer Part Number
ATtiny861 Automotive
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT90CAN128_AUTOMOTIVE.pdf
(225 pages)
2.ATTINY261_AUTOMOTIVE.pdf
(11 pages)
3.ATTINY261_AUTOMOTIVE.pdf
(16 pages)
4.ATTINY261_AUTOMOTIVE.pdf
(226 pages)
Specifications of ATtiny861 Automotive
Flash (kbytes)
8 Kbytes
Pin Count
20
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
8
Hardware Qtouch Acquisition
No
Max I/o Pins
16
Ext Interrupts
16
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.5
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 150
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
6
Input Capture Channels
1
Pwm Channels
6
32khz Rtc
No
Calibrated Rc Oscillator
Yes
- AT90CAN128_AUTOMOTIVE PDF datasheet
- ATTINY261_AUTOMOTIVE PDF datasheet #2
- ATTINY261_AUTOMOTIVE PDF datasheet #3
- ATTINY261_AUTOMOTIVE PDF datasheet #4
- Current page: 149 of 226
- Download datasheet (5Mb)
19.6
7753F–AVR–01/11
Changing Channel or Reference Selection
Figure 19-6. ADC Timing Diagram, Auto Triggered Conversion
Figure 19-7. ADC Timing Diagram, Free Running Conversion
Table 19-1.
The MUX5:0 and REFS2:0 bits in the ADMUX Register are single buffered through a temporary
register to which the CPU has random access. This ensures that the channels and reference
selection only takes place at a safe point during the conversion. The channel and reference
selection is continuously updated until a conversion is started. Once the conversion starts, the
channel and reference selection is locked to ensure a sufficient sampling time for the ADC. Con-
tinuous updating resumes in the last ADC clock cycle before the conversion completes (ADIF in
ADCSRA is set).
Condition
First conversion
Normal conversions
Auto Triggered conversions
Cycle Number
ADC Clock
Trigger
Source
ADATE
ADIF
ADCH
ADCL
Prescaler
Reset
ADC Conversion Time
MUX and REFS
Update
Cycle Number
ADC Clock
ADSC
ADIF
ADCH
ADCL
1
2
Sample & Hold
(Cycles from Start of Conversion)
Conversion
Complete
3
One Conversion
Sample &
Hold
11
ATtiny261/ATtiny461/ATtiny861
4
12
5
13.5
1.5
6
13
2
7
One Conversion
Next Conversion
1
Sign and MSB of Result
LSB of Result
8
2
MUX and REFS
Update
9
3
10
Conversion
Complete
Sample & Hold
11
4
Total Conversion Time (Cycles)
12
13
Sign and MSB of Result
13.5
25
13
LSB of Result
Next Conversion
1
Prescaler
Reset
2
149
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