ATtiny861 Automotive Atmel Corporation, ATtiny861 Automotive Datasheet - Page 195
ATtiny861 Automotive
Manufacturer Part Number
ATtiny861 Automotive
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT90CAN128_AUTOMOTIVE.pdf
(225 pages)
2.ATTINY261_AUTOMOTIVE.pdf
(11 pages)
3.ATTINY261_AUTOMOTIVE.pdf
(16 pages)
4.ATTINY261_AUTOMOTIVE.pdf
(226 pages)
Specifications of ATtiny861 Automotive
Flash (kbytes)
8 Kbytes
Pin Count
20
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
8
Hardware Qtouch Acquisition
No
Max I/o Pins
16
Ext Interrupts
16
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.5
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 150
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
6
Input Capture Channels
1
Pwm Channels
6
32khz Rtc
No
Calibrated Rc Oscillator
Yes
- AT90CAN128_AUTOMOTIVE PDF datasheet
- ATTINY261_AUTOMOTIVE PDF datasheet #2
- ATTINY261_AUTOMOTIVE PDF datasheet #3
- ATTINY261_AUTOMOTIVE PDF datasheet #4
- Current page: 195 of 226
- Download datasheet (5Mb)
7753F–AVR–01/11
Figure 23-5. Parallel Programming Timing, Reading Sequence (within the Same Page) with
Note:
Table 23-7.
Notes:
Symbol
V
I
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
PP
DVXH
XLXH
XHXL
XLDX
XLWL
BVPH
PHPL
PLBX
WLBX
PLWL
BVWL
WLWH
WLRL
WLRH
WLRH_CE
XLOL
BVDV
OLDV
OHDZ
PP
PAGEL/BS1
XA1/BS2
1. The timing requirements shown in
1. t
2. t
XTAL1
DATA
XA0
OE
ing operation.
commands.
WLRH_CE
Parameter
Programming Enable Voltage
Programming Enable Current
Data and Control Valid before XTAL1 High
XTAL1 Low to XTAL1 High
XTAL1 Pulse Width High
Data and Control Hold after XTAL1 Low
XTAL1 Low to WR Low
BS1 Valid before PAGEL High
PAGEL Pulse Width High
BS1 Hold after PAGEL Low
BS2/1 Hold after WR Low
PAGEL Low to WR Low
BS1 Valid to WR Low
WR Pulse Width Low
WR Low to RDY/BSY Low
WR Low to RDY/BSY High
WR Low to RDY/BSY High for Chip Erase
XTAL1 Low to OE Low
BS1 Valid to DATA valid
OE Low to DATA Valid
OE High to DATA Tri-stated
WLRH
Timing Requirements
Parallel Programming Characteristics, V
is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock bits
is valid for the Chip Erase command.
ADDR0 (Low Byte)
LOAD ADDRESS
(LOW BYTE)
t
XLOL
t
OLDV
ATtiny261/ATtiny461/ATtiny861
(1)
(1)
Figure 23-3
(LOW BYTE)
DATA (Low Byte)
READ DATA
(2)
(i.e., t
t
BVDV
CC
= 5V ± 10%
DVXH
11.5
Min
200
150
150
150
3.7
7.5
67
67
67
67
67
67
67
0
0
0
0
(HIGH BYTE)
READ DATA
, t
DATA (High Byte)
XHXL
, and t
Typ
t
OHDZ
XLDX
) also apply to read-
LOAD ADDRESS
(LOW BYTE)
Max
12.5
250
250
250
250
4.5
1
9
ADDR1 (Low Byte)
Units
ms
ms
µA
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
V
195
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