ATxmega16D4 Atmel Corporation, ATxmega16D4 Datasheet - Page 137

• Manufacturer Part Number: ATxmega16D4
• Manufacturer: Atmel Corporation

Specifications of ATxmega16D4

• Flash (kbytes): 16 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Speed: No
• Usb Interface: No
• Spi: 4
• Twi (i2c): 2
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 12
• Adc Speed (ksps): 200
• Analog Comparators: 2
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 2
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 14
• Input Capture Channels: 14
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

12.11 Register Description
12.11.1
12.11.2
8210B–AVR–04/10
CTRLA - Control Register A
CTRLB - Control Register B
• Bit 7:4 - Reserved bits
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 3:0 - CLKSEL[3:0]: Clock Select
These bits select clock source for the Timer/Counter according to
CLKSEL=0001 must be set to ensure a correct output from the waveform generator when the
Hi-Res extension is enabled.
Table 12-2.
• Bit 7:4 – CCxEN: Compare or Capture Enable
Setting these bits in FRQ or PWM waveform generation mode of operation will override of the
port output register for the corresponding OCn output pin.
When input capture operation is selected the CCxEN bits enables the capture operation for the
corresponding CC channel.
Bit
+0x01
Read/Write
Initial Value
Bit
+0x00
Read/Write
Initial Value
CLKSEL[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1xxx
CCDEN
R/W
Clock Select
7
0
R
7
–
0
Group Configuration
CCCEN
R/W
R
6
0
6
–
0
DIV1024
DIV256
EVCHn
DIV64
DIV1
DIV2
DIV4
DIV8
OFF
CCBEN
R/W
R
5
0
5
–
0
CCAEN
R/W
R
4
0
4
–
0
Description
None (i.e, Timer/Counter in ‘OFF’ state)
Prescaler: clk
Prescaler: clk/2
Prescaler: clk/4
Prescaler: clk/8
Prescaler: clk/64
Prescaler: clk/256
Prescaler: clk/1024
Event channel n, n= [0,...,7]
R/W
R
3
0
3
–
0
R/W
R/W
2
0
2
0
CLKSEL[3:0]
Table
WGMODE[2:0]
R/W
R/W
1
0
1
0
12-2.
XMEGA D
R/W
R/W
0
0
0
0
CTRLA
CTRLB
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