ATxmega16D4 Atmel Corporation, ATxmega16D4 Datasheet - Page 194

• Manufacturer Part Number: ATxmega16D4
• Manufacturer: Atmel Corporation

Specifications of ATxmega16D4

• Flash (kbytes): 16 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Speed: No
• Usb Interface: No
• Spi: 4
• Twi (i2c): 2
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 12
• Adc Speed (ksps): 200
• Analog Comparators: 2
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 2
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 14
• Input Capture Channels: 14
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

17.3
17.4
8210B–AVR–04/10
Master Mode
Slave Mode
In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure
correct sampling of this clock signal, the minimum low and high periods must be:
Low period: longer than 2 CPU clock cycles.
High period: longer than 2 CPU clock cycles.
When the SPI module is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is
overridden according to
from software to have the correct direction according to the application.
Table 17-1.
When configured as a Master, the SPI interface has no automatic control of the SS line. The SS
pin must be configured as output, and controlled by user software. If the bus consists of several
SPI slaves and/or masters, a SPI master can use general I/O pins to control the SS line to each
of the slaves on the bus.
Writing a byte to the Data register starts the SPI clock generator, and the hardware shifts the
eight bits into the selected Slave. After shifting one byte, the SPI clock generator stops and the
SPI Interrupt Flag is set. The Master may continue to shift the next byte by writing new data to
the Data register, or signal the end of transfer by pulling the SS line high. The last incoming byte
will be kept in the Buffer Register.
If the SS pin is configured as an input, it must be held high to ensure Master operation. If the SS
pin is input and being driven low by external circuitry, the SPI module will interpret this as
another master trying to take control of the bus. To avoid bus contention, the Master will take the
following action:
When configured as a Slave, the SPI interface will remain sleeping with MISO tri-stated as long
as the SS pin is driven high. In this state, software may update the contents of the Data register,
but the data will not be shifted out by incoming clock pulses on the SCK pin until the SS pin is
driven low. If SS is driven low and assuming the MISO pin is configured as output, the Slave will
start to shift out data on the first SCK clock pulse. As one byte has been completely shifted, the
SPI Interrupt Flag is set. The Slave may continue to place new data to be sent into the Data reg-
ister before reading the incoming data. The last incoming byte will be kept in the Buffer Register.
When SS is driven high, the SPI logic is reset, and the SPI Slave will not receive any data. Any
partially received packet in the shift register will be dropped.
1. The Master enters Slave mode.
2. The SPI Interrupt Flag is set.
MOSI
MISO
SCK
Pin
SS
Direction, Master SPI
User Defined
Input
User Defined
User Defined
SPI pin overrides
Table
17-1. The pins with user defined direction, must be configured
Direction, Slave SPI
Input
User Defined
Input
Input
XMEGA D
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