ATxmega256A3BU Atmel Corporation, ATxmega256A3BU Datasheet - Page 13

• Manufacturer Part Number: ATxmega256A3BU
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3BU

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 47
• Ext Interrupts: 49
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 8
• Twi (i2c): 2
• Uart: 6
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

3.12.1
3.12.2
3.13
8331A–AVR–07/11
Fuse Lock
Sequence for write operation to protected I/O registers
Sequence for execution of protected SPM/LPM
the fuses and signature row. This is handled globally by the configuration change protection
(CCP) register. Changes to the protected I/O registers or bits, or execution of protected instruc-
tions, are only possible after the CPU writes a signature to the CCP register. The different
signatures are described in the register description.
There are two modes of operation: one for protected I/O registers, and one for the protected
instructions, SPM/LPM.
Once the correct signature is written by the CPU, interrupts will be ignored for the duration of the
configuration change enable period. Any interrupt request (including non-maskable interrupts)
during the CCP period will set the corresponding interrupt flag as normal, and the request is kept
pending. After the CCP period is completed, any pending interrupts are executed according to
their level and priority. DMA requests are still handled, but do not influence the protected config-
uration change enable period. A signature written by DMA is ignored.
For some system-critical features, it is possible to program a fuse to disable all changes to the
associated I/O control registers. If this is done, it will not be possible to change the registers from
the user software, and the fuse can only be reprogrammed using an external programmer.
Details on this are described in the datasheet module where this feature is available.
1. The application code writes the signature that enable change of protected I/O registers
2. Within four instruction cycles, the application code must write the appropriate data to
1. The application code writes the signature for the execution of protected SPM/LPM to
2. Within four instruction cycles, the application code must execute the appropriate
to the CCP register.
the protected register. Most protected registers also contain a write enable/change
enable bit. This bit must be written to one in the same operation as the data are written.
The protected change is immediately disabled if the CPU performs write operations to
the I/O register or data memory or if the SPM, LPM, or SLEEP instruction is executed.
the CCP register.
instruction. The protected change is immediately disabled if the CPU performs write
operations to the data memory or if the SLEEP instruction is executed.
Atmel AVR XMEGA AU
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