ATxmega256A3BU Atmel Corporation, ATxmega256A3BU Datasheet - Page 25

• Manufacturer Part Number: ATxmega256A3BU
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3BU

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 47
• Ext Interrupts: 49
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 8
• Twi (i2c): 2
• Uart: 6
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

4.13
4.14
4.15
4.15.1
4.15.2
4.15.3
8331A–AVR–07/11
JTAG Disable
I/O Memory Protection
Register Description – NVM Controller
ADDR0
ADDR1 – Nonvolatile Memory Address Register 1
ADDR2 – Nonvolatile Memory Address Register 2
–
Nonvolatile Memory Address Register 0
It is possible to disable the JTAG interface from the application software. This will prevent all
external JTAG access to the device until the next device reset or until JTAG is enabled again
from the application software. As long as JTAG is disabled, the I/O pins required for JTAG can
be used as normal I/O pins.
Some features in the device are regarded as critical for safety in some applications. Due to this,
it is possible to lock the I/O register related to the clock system, the event system and the
advanced waveform extensions. As long as the lock is enabled, all related I/O registers are
locked and they can not be written from the application software. The lock registers themselves
are protected by the configuration change protection mechanism. For details refer to
tion Change Protection” on page
The ADDR0, ADDR1, and ADDR2 registers represent the 24-bit value ADDR. This is used for
addressing all NVM sections for read, write, and CRC operations.
• Bit 7:0 – ADDR[7:0]: NVM Address Register Byte 0
This register gives the address low byte when accessing NVM locations.
• Bit 7:0 – ADDR[15:8]: NVM Address Register Byte 1
This register gives the address high byte when accessing NVM locations.
• Bit 7:0 – ADDR[23:16]: NVM Address Register Byte 2
This register gives the address extended byte when accessing NVM locations.
Bit
+0x00
Read/Write
Initial Value
Bit
+0x01
Read/Write
Initial Value
Bit
+0x02
Read/Write
Initial Value
R/W
R/W
R/W
7
0
7
0
7
0
R/W
R/W
R/W
6
0
6
0
6
0
12.
R/W
R/W
R/W
5
0
5
0
5
0
R/W
R/W
R/W
4
0
4
0
4
0
ADDR[23:16]
ADDR[15:8]
ADDR[7:0]
Atmel AVR XMEGA AU
R/W
R/W
R/W
3
0
3
0
3
0
R/W
R/W
R/W
2
0
2
0
2
0
R/W
R/W
R/W
1
0
1
0
1
0
R/W
R/W
R/W
0
0
0
0
0
0
”Configura-
ADDR0
ADDR1
ADDR2
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