ATxmega256A3BU Atmel Corporation, ATxmega256A3BU Datasheet - Page 85

• Manufacturer Part Number: ATxmega256A3BU
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3BU

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 47
• Ext Interrupts: 49
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 8
• Twi (i2c): 2
• Uart: 6
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

7.4.2.3
7.5
8331A–AVR–07/11
System Clock Selection and Prescalers
32.768kHz Crystal Oscillator
Figure 7-3.
A 32.768kHz crystal oscillator can be connected between the TOSC1 and TOSC2 pins and
enables a dedicated low frequency oscillator input circuit. A typical connection is shown in
ure 7-4 on page
oscillator can be used as a clock source for the system clock and RTC, and as the DFLL refer-
ence clock.
Figure 7-4.
Two capacitors, C1 and C2, may be added to match the required load capacitance for the con-
nected crystal. For details on recommened TOSC characteristics and capacitor laod, refer to
device datasheets.
All the calibrated internal oscillators, the external clock sources (XOSC), and the PLL output can
be used as the system clock source. The system clock source is selectable from software, and
can be changed during normal operation. Built-in hardware protection prevents unsafe clock
switching. It is not possible to select a non-stable or disabled oscillator as the clock source, or to
disable the oscillator currently used as the system clock source. Each oscillator option has a sta-
tus flag that can be read from software to check that the oscillator is ready.
The system clock is fed into a prescaler block that can divide the clock signal by a factor from 1
to 2048 before it is routed to the CPU and peripherals. The prescaler settings can be changed
from software during normal operation. The first stage, prescaler A, can divide by a factor of
from 1 to 512. Then, prescalers B and C can be individually configured to either pass the clock
through or combine divide it by a factor from 1 to 4. The prescaler guarantees that derived
clocks are always in phase, and that no glitches or intermediate frequencies occur when chang-
ing the prescaler setting. The prescaler settings are updated in accordance with the rising edge
of the slowest clock.
External clock drive configuration.
32.768kHz crystal oscillator connection.
85. A low power mode with reduced voltage swing on TOSC2 is available. This
Purpose
External
General
Signal
Clock
I/O
C1
C2
Atmel AVR XMEGA AU
XTAL2
XTAL1
TOSC2
TOSC1
GND
Fig-
85