ATxmega256A3BU Atmel Corporation, ATxmega256A3BU Datasheet - Page 203

• Manufacturer Part Number: ATxmega256A3BU
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3BU

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 47
• Ext Interrupts: 49
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 8
• Twi (i2c): 2
• Uart: 6
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

16.3
8331A–AVR–07/11
Port Override
output pairs go through a dead-time insertion (DTI) unit that generates the non-inverted low side
(LS) and inverted high side (HS) of the WG output with dead-time insertion between LS and HS
switching. The DTI output will override the normal port value according to the port override set-
ting. Refer to
The pattern generation unit can be used to generate a synchronized bit pattern on the port it is
connected to. In addition, the WG output from compare channel A can be distributed to and
override all the port pins. When the pattern generator unit is enabled, the DTI unit is bypassed.
The fault protection unit is connected to the event system, enabling any event to trigger a fault
condition that will disable the AWeX output. The event system ensures predictable and instant
fault reaction, and gives flexibility in the selection of fault triggers.
The port override logic is common for all the timer/counter extensions.
shows a schematic diagram of the port override logic. When the dead-time enable (DTIENx) bit
is set, the timer/counter extension takes control over the pin pair for the corresponding channel.
Given this condition, the output override enable (OOE) bits take control over the CCxEN bits.
”I/O Ports” on page 139
for more details.
Atmel AVR XMEGA AU
Figure 16-2 on page 204
203