ATxmega256A3BU Atmel Corporation, ATxmega256A3BU Datasheet - Page 359

• Manufacturer Part Number: ATxmega256A3BU
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3BU

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 47
• Ext Interrupts: 49
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 8
• Twi (i2c): 2
• Uart: 6
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

8331A–AVR–07/11
The result registers are 16-bit wide stored as a right adjusted 16-bit value. Right adjusted means
that the 8LSB is found in the low byte. A 12-bit result can be represented both left- or right
adjusted. Left adjusted means that the 8MSB are found in the high byte.
When the ADC is in signed mode, the msb represents the sign bit. In 12-bit right adjusted mode,
the sign bit (bit 11) is padded to bits 12-15 to create a signed 16-bit number directly. In 8-bit
mode, the sign bit (bit 7) is padded to the entire high byte.
Figure 28-9 on page 359
nal input range and the result representation with 12-bit right adjusted mode.
Figure 28-9. Signed differential input (with gain), input range, and result representation
Figure 28-10. Signed single ended and internal input, input range, and result representation
Figure 28-11. Unsigned single ended and internal input, input range, and result representation
VREF
VREF
-VREF
-VREF
GAIN
VREF
GAIN
0 V
0 V
GND
−
Δ
V
to
Figure 28-11 on page 359
VINN
VINN = GND
=
VREF
2
VINP
VINN
RES
VINP
VINP
−
Δ
V
4095
4094
4093
-2045
-2046
-2047
-2048
-2045
-2046
-2047
-2048
Dec
2047
2046
2045
203
202
201
200
2047
2046
2045
Dec
Dec
...
...
0
...
-1
-2
...
...
-1
-2
...
3
2
1
0
3
2
1
0
Atmel AVR XMEGA AU
Hex
FFF
FFE
FFD
0CB
0CA
0C9
0C8
7FD
FFE
Hex
7FE
7FD
FFF
FFE
Hex
7FF
7FE
FFF
7FF
803
802
801
800
803
802
801
800
shows the different input options, the sig-
...
0
...
...
...
...
3
2
1
0
3
2
1
0
1111 1111 1111
1111 1111 1110
1111 1111 1101
0000 1100 1011
0000 1100 1010
0000 1100 1001
0000 1100 1000
0000 0000 0000
0111 1111 1111
0111 1111 1110
0111 1111 1101
0000 0000 0011
0000 0000 0010
0000 0000 0001
0000 0000 0000
1111 1111 1111
1111 1111 1110
1000 0000 0011
1000 0000 0010
1000 0000 0001
1000 0000 0000
0111 1111 1111
0111 1111 1110
0111 1111 1101
0000 0000 0011
0000 0000 0010
0000 0000 0001
0000 0000 0000
1111 1111 1111
1111 1111 1110
1000 0000 0011
1000 0000 0010
1000 0000 0001
1000 0000 0000
Binary
Binary
Binary
...
...
...
...
...
0000 1111 1111 1111
0000 1111 1111 1110
0000 1111 1111 1101
0000 0000 1100 1011
0000 0000 1100 1010
0000 0000 1100 1001
0000 0000 1100 1000
0000 0000 0000 0000
16-bit result register
0000 0111 1111 1111
0000 0111 1111 1110
0000 0111 1111 1101
0000 0000 0000 0011
0000 0000 0000 0010
0000 0000 0000 0001
0000 0000 0000 0000
1111 1111 1111 1111
1111 1111 1111 1110
1111 1000 0000 0011
1111 1000 0000 0010
1111 1000 0000 0001
1111 1000 0000 0000
16-bit result register
0000 0111 1111 1111
0000 0111 1111 1110
0000 0111 1111 1101
0000 0000 0000 0011
0000 0000 0000 0010
0000 0000 0000 0001
0000 0000 0000 0000
1111 1111 1111 1111
1111 1111 1111 1110
1111 1000 0000 0011
1111 1000 0000 0010
1111 1000 0000 0001
1111 1000 0000 0000
16-bit result register
...
...
...
...
...
359