ATxmega256A3BU Atmel Corporation, ATxmega256A3BU Datasheet - Page 318
ATxmega256A3BU
Manufacturer Part Number
ATxmega256A3BU
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega256A3BU
Flash (kbytes)
256 Kbytes
Pin Count
64
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
47
Ext Interrupts
49
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
8
Twi (i2c)
2
Uart
6
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
16
Eeprom (bytes)
4096
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
7
Output Compare Channels
22
Input Capture Channels
22
Pwm Channels
22
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega256A3BU-AU
Manufacturer:
ST
Quantity:
12 000
Company:
Part Number:
ATxmega256A3BU-MH
Manufacturer:
AAT
Quantity:
400
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25.4.1
8331A–AVR–07/11
Key and State Memory
The following setup and use procedure is recommended:
If more than one block is to be encrypted or decrypted, repeat the procedure from step 3.
When the encryption/decryption procedure is complete, the AES interrupt flag is set and an
optional interrupt is generated.
The AES key and state memory are both 16 x 8-bit memories that are accessible through the
KEY and STATE registers, respectively.
Each memory has two 4-bit address pointers used to address the memory for read and write,
respectively. The initial value of the pointers is zero. After a read or write operation to the STATE
or KEY register, the appropriate pointer is automatically incremented. Accessing (read or write)
the control register (CTRL) will reset all pointers to zero. A pointer overflow (a sequential read or
write done more than 16 times) will also set the affected pointer to zero. The pointers are not
accessible from software. Read and write memory pointers are both incremented during write
operations in XOR mode.
Access to the KEY and STATE registers is possible only when encryption/decryption is not in
progress.
Figure 25-2. The state memory with pointers and register.
The state memory contains the AES state throughout the encryption/decryption process. The ini-
tial value of the state is the initial data (i.e., plaintext in the encryption mode, and ciphertext in the
decryption mode). The last value of the state is the encrypted/decrypted data.
1. Enable the AES interrupt (optional).
2. Select the AES direction to encryption or decryption.
3. Load the key data block into the AES key memory.
4. Load the data block into the AES state memory.
5. Start the encryption/decryption operation.
4-bit state write
address pointer
reset or access
to AES Control
Reset pointer
I/O Data Bus
XOR
STATE
14
15
0
1
-
xor
Atmel AVR XMEGA AU
STATE[read pointer]
address pointer
4-bit state read
reset or access
to AES Control
Reset pointer
318
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