SAM3N00A Atmel Corporation, SAM3N00A Datasheet - Page 311

• Manufacturer Part Number: SAM3N00A
• Manufacturer: Atmel Corporation

21.6
21.7
11011A–ATARM–04-Oct-10
System I/O Configuration
Write Protect Registers
more master’s requests with the same priority are active at the same time, the master with the
highest number is serviced first.
For each slave, the priority of each master may be defined through the Priority Registers for
Slaves (MATRIX_PRAS and MATRIX_PRBS).
The System I/O Configuration register (CCFG_SYSIO) allows to configure some I/O lines in
System I/O mode (such as JTAG, ERASE, etc...) or as general purpose I/O lines. Enabling or
disabling the corresponding I/O lines in peripheral mode or in PIO mode (PIO_PER or PIO_PDR
registers) in the PIO controller as no effect. However, the direction (input or output), pull-up, pull-
down and other mode control is still managed by the PIO controller.
To prevent any single software error that may corrupt MATRIX behavior, the entire MATRIX
address space from address offset 0x000 to 0x1FC can be write-protected by setting the
WPEN bit in the MATRIX Write Protect Mode Register (MATRIX_WPMR).
If a write access to anywhere in the MATRIX address space from address offset 0x000 to 0x1FC
is detected, then the WPVS flag in the MATRIX Write Protect Status Register (MATRIX_WPSR)
is set and the field WPVSRC indicates in which register the write access has been attempted.
The WPVS flag is reset by writing the MATRIX Write Protect Mode Register (MATRIX_WPMR)
with the appropriate access key WPKEY.
SAM3N
311